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No instruction set computing (NISC) is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low-level control of hardware resources.
NISC is a statically scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that theoperation scheduling andHazard handling are done by acompiler. The term "horizontal nanocoded" means that NISC does not have any predefinedinstruction set ormicrocode. The compiler generates nanocodes which directly controlfunctional units,registers andmultiplexers of a givendatapath. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:
The instruction set and controller ofprocessors are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.
Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designer's productivity is improved significantly.
Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable tohigh level synthesis (HLS) orC to HDL synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).
Incomputer science,zero instruction set computer (ZISC) refers to acomputer architecture based solely onpattern matching and absence of(micro-)instructions in the classical[clarification needed] sense. These chips are known for being thought of as comparable to theneural networks, being marketed for the number of "synapses" and "neurons".[1] Theacronym ZISC alludes toreduced instruction set computer (RISC).[citation needed]
ZISC is a hardware implementation ofKohonen networks (artificial neural networks) allowing massively parallel processing of very simple data (0 or 1). This hardware implementation was invented by Guy Paillet[2] and Pascal Tannhof (IBM),[3][2] developed in cooperation with the IBM chip factory ofEssonnes, in France, and was commercialized by IBM.
The ZISC architecture alleviates thememory bottleneck[clarification needed] by blending pattern memory with pattern learning and recognition logic.[how?] Their massivelyparallel computing solves the"winner takes all problem in action selection"[clarification needed fromWinner-takes-all problem inNeural Networks] by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.[4]
According toTechCrunch, software emulations of these types of chips are currently used for image recognition by many large tech companies, such asFacebook andGoogle. When applied to other miscellaneous pattern detection tasks, such as with text, results are said to be produced in microseconds even with chips released in 2007.[1]
Junko Yoshida, of theEE Times, compared the NeuroMem chip with "The Machine", a machine capable of being able to predict crimes from scanning people's faces from the television seriesPerson of Interest, describing it as "the heart ofbig data" and "foreshadow[ing] a real-life escalation in the era of massive data collection".[5]
In the past, microprocessor design technology evolved fromcomplex instruction set computer (CISC) toreduced instruction set computer (RISC). In the early days of the computer industry, compiler technology did not exist and programming was done inassembly language. To make programming easier, computer architects created complex instructions which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.
As compiler and memory technologies advanced, RISC architectures were introduced. RISC architectures need more instruction memory and require a compiler to translate high-level languages to RISC assembly code. Further advancement of compiler and memory technologies leads to emergingvery long instruction word (VLIW) processors, where the compiler controls the schedule of instructions and handles data hazards.
NISC is a successor of VLIW processors. In NISC, the compiler has both horizontal and vertical control of the operations in the datapath. Therefore, the hardware is much simpler. However the control memory size is larger than the previous generations. To address this issue, low-overhead compression techniques can be used.
