AMD Zen 3

General information
Launched	November 5, 2020; 4 years ago (November 5, 2020)
Designed by	AMD
Common manufacturers	TSMC GlobalFoundries
CPUID code	Family 19h
Cache
L1cache	64 KB (per core): 32 KB instructions 32 KB data
L2 cache	512 KB (per core)
L3 cache	32 MB (perCCD) 96 MB (perCCD with 3D V-Cache) 16 MB (in APUs)
Architecture and classification
Technology node	TSMCN7 TSMCN6
Instruction set	AMD64 (x86-64)
Physical specifications
Transistors	6.24 billion (1× CCD) or 10.39 billion (2× CCD) (4.15 billion per 7 nm 8-core "CCD" & 2.09 billion for the 12 nm "I/O die")[1]
Cores	Desktop: 4 to 16 Workstation: 16 to 64 Server: 16 to 64
Package	Package FP6
Sockets	Socket AM4 Socket SP3 Socket sWRX8
Products, models, variants
Product code names	Desktop Vermeer (w/oiGPU) Cézanne (APU) Chagall Thin & Light Mobile Cézanne Barcelo Barcelo-R High-End Mobile Cézanne Server Milan Milan-X
History
Predecessor	Zen 2
Successors	Zen 3+ Zen 4
Support status
Supported

Zen 3 is the name for aCPUmicroarchitecture byAMD, released on November 5, 2020.^[2][3] It is the successor toZen 2 and usesTSMC's7 nm process for the chiplets andGlobalFoundries's14 nm process for the I/O die on the server chips and 12 nm for desktop chips.^[4] Zen 3 powersRyzen 5000 mainstream desktop processors (codenamed "Vermeer") andEpyc server processors (codenamed "Milan").^[5][6] Zen 3 is supported on motherboards with500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes.^[7] Zen 3 is the last microarchitecture before AMD switched toDDR5 memory and new sockets, which are AM5 for the desktop "Ryzen" chips alongside SP5 and SP6 for the EPYC server platform and sTRX8.^[3] According to AMD, Zen 3 has a 19% higherinstructions per cycle (IPC) on average thanZen 2.

On April 1, 2022, AMD released the new Ryzen 6000 series for laptops/mobile, using an improvedZen 3+ architecture featuring notable architectural improvements to power efficiency and power management.^[8] And slightly later, on April 20, 2022, AMD would also release the Ryzen 7 5800X3D desktop processor, which increased gaming performance by around +15% on average by using for the very first time in a PC product, a 3D vertically stacked L3 cache. Specifically in the form of a 64MB L3 cache "3D V Cache" die made on the same TSMC N7 process as the 8-core Zen 3 CCD which it gets direct copper to copper hybrid bonded to.^[9]

As the first largely "ground up redesign" of the Zen CPU core since the architecture family's original release in early 2017 with Zen 1/Ryzen 1000, Zen 3 was a significant architectural improvement over its predecessors; having a very significantIPC increase of +19% over the prior Zen 2 architecture in addition to being capable of reaching higher clock speeds.^[10]

Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing theI/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8CPU cores and 32 MB of sharedL3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores paired with 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through theInfinity Fabric.^[10]

Zen 3 (along with AMD'sRDNA2 GPUs) also implemented ResizableBAR, an optional feature introduced in PCIe 2.0, that was branded asSmart Access Memory (SAM). This technology allows CPU to directly access all of compatible video card'sVRAM.^[11] Intel and Nvidia have since implemented this feature as well.^[12]

• 
  A de-lidded Ryzen 5 5600X. Only one 6-core CCD is present. The contacts for a second CCD are visible.
• 
  Close-up of the CCD, taken under infrared lighting. This die was damaged by the de-lidding process.
• 
  Close-up of the I/O die

In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs. Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.^[13]

On April 20, 2022, AMD released the R7 5800X3D. It features, for the first time in a desktop PC product, 3D-stacked vertical L3 cache. Its extra 64MB comes via a TSMC N7 (7nm) "3D V Cache" die direct copper to copper hybrid bonded right on top of the 8-core Zen 3 CCD's usual 32MB, increasing the CPU's total L3 cache capacity to 96MB and bringing significant performance improvements for gaming in particular; now rivalling contemporary high-end consumer processors while being much more power efficient and running on older, cheaper motherboards using affordable DDR4 memory.^[9] And despite now spanning multiple dies and being three times larger (96MB vs 32MB), the L3 cache's performance remains nearly identical; with X3D only adding around ≈+2ns via an additional three to four cycles of latency.^[14] It would later be followed by the Ryzen 5 5600X3D and Ryzen 7 5700X3D for lower-end market segments, and succeeded by the Ryzen 7000X3D family of 3D V Cache equipped Zen 4 processors on the newer socket AM5 platform.

Zen 3 has made the following improvements over Zen 2:^[13][15]

• An increase of 19% ininstructions per clock
• The base corechiplet has a single eight-core complex (versus two four-core complexes in Zen 2)
• A unified 32MB L3 cache pool equally available to all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex.
  • On mobile: A unified 16MB L3
• A unified 8-core CCX (from 2x 4-core CCX per CCD)
• Increasedbranch prediction bandwidth. L1 branch target buffer size increased to 1024 entries (vs 512 in Zen 2)
• New instructions
  • VAES – 256-bit Vector AES instructions
  • INVLPGB – Broadcast TLB flushing
  • CET_SS – Control-flow Enforcement Technology /Shadow Stack
• Improved integer units
  • 96 entry integer scheduler (up from 92)
  • 192 entry physical register file (up from 180)
  • 10 issue per cycle (up from 7)
  • 256 entryreorder-buffer (up from 224)
  • fewer cycles for DIV/IDIV ops (10...20 from 16...46)
• Improved floating point units
  • 6μOP dispatch width (up from 4)
  • FMA latency reduced by 1 cycle (down from 5 to 4)
• Additional 64MB 3D vertically stacked dense library L3 cache (in -X3D models)

This section is empty. You can help byadding to it.(March 2023)

APU features table

On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.^[2]

The Ryzen 5000 series desktop CPUs are codenamedVermeer. The models in the second table are based onCezanneAPUs with theintegrated GPU disabled. Meanwhile the Ryzen Threadripper Pro 5000 series were codenamedChagall.

Common features of Ryzen 5000 desktop CPUs:

• Socket:AM4.
• All the CPUs supportDDR4-3200 indual-channel mode.
• All the CPUs support 24PCIe 4.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• L1cache: 64 KB per core (32 KB data + 32 KB instruction).
• L2 cache: 512 KB per core.
• Fabrication process:TSMC7FF.

Common features of Ryzen 5000 (Cezanne) desktop CPUs:

• Socket:AM4.
• CPUs supportDDR4-3200 indual-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• CPUs support 24PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• Fabrication process:TSMC7FF.

5100, 5500, and 5700 have no ECC support like non-Pro Ryzen 5000 Desktop APUs.

Common features of Ryzen 5000 workstation CPUs:

• Socket:sWRX8.
• All the CPUs supportDDR4-3200 inocta-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 128PCIe 4.0 lanes. 8 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• Fabrication process:TSMC7FF.

Common features of Ryzen 5000 desktop APUs:

• Socket:AM4.
• All the CPUs supportDDR4-3200 indual-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 24PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integratedGCN 5th generation GPU.
• Fabrication process:TSMC7FF.

Common features of Ryzen 7030 notebook APUs:

• Socket: FP6.
• All the CPUs supportDDR4-3200 orLPDDR4-4266 indual-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16PCIe 3.0 lanes.
• Native USB 4 (40Gbps) Ports: 0
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• Includes integratedGCN 5th generation GPU.
• Fabrication process:TSMCN7 FinFET.

TheEpyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using theSP3 socket.^[6] Epyc Milan was released on March 15, 2021.^[65]

Common features:

• SP3 socket
• Zen 3 microarchitecture
• TSMC7 nm process for the compute and cache dies,GloFo14 nm process for the I/O die
• MCM with oneI/O Die (IOD) and multipleCore Complex Dies (CCD) for compute, one core complex (CCX) per CCD chiplet
• Eight-channel DDR4-3200
• 128 PCIe 4.0 lanes per socket, 64 of which are used forInfinity Fabric in 2P platforms
• 7003X series models include 64 MiB L3 cache diesstacked on top of the compute dies (3D V-Cache)
• 7003P series models are restricted to uniprocessor operation (1P)

Zen 3+ is the codename for a refresh of the Zen 3 microarchitecture, which focuses on power efficiency improvements. It was released in April 2022 with the Ryzen 6000 series of mobile processors.

Zen 3+ has 50 new or enhanced power management features over Zen 3, and also provides an adaptive power management framework, as well as new deep sleep states. Altogether, this brings improvements to efficiency both during idle, and when under load, with up to 30% performance-per-watt increase over Zen 3, as well as longer battery life.^[67][68]

IPC is identical to that of Zen 3; the performance improvements of Ryzen 6000 over Ryzen 5000 mobile processors stem from it having a higher efficiency (hence more performance in power-constrained form factors like laptops), as well as the increased clock speeds from being built on the smaller TSMC N6 node.^[69]

TheRembrandt implementation of Zen 3+ also has support for DDR5 and LPDDR5 memory.

On April 1, 2022, AMD released the Ryzen 6000 series of mobile APUs, codenamed Rembrandt. It introduces PCIe 4.0 and DDR5/LPDDR5 for the first time in an APU for the laptop and also introduced RDNA2 integrated graphics to the PC. It is built on TSMC's 6 nm node.^[8]

Common features of Ryzen 6000 notebook APUs:

• Socket: FP7, FP7r2.
• All the CPUs supportDDR5-4800 orLPDDR5-6400 indual-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16PCIe 4.0 lanes.
• Native USB 4 (40Gbps) Ports: 2
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• Includes integratedRDNA 2 GPU.
• Fabrication process:TSMCN6 FinFET.

Rembrandt-R is the codename for a refresh of Rembrandt codenamed processors, released as the Ryzen 7035 series of mobile APUs in January 2023.

Common features of Ryzen 7035 notebook APUs:

• Socket: FP7, FP7r2.
• All the CPUs supportDDR5-4800 orLPDDR5-6400 indual-channel mode.
• L1cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16PCIe 4.0 lanes.
• Native USB 4 (40Gbps) Ports: 0
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• Includes integratedRDNA 2 GPU.
• Fabrication process:TSMCN6 FinFET.

• AMD microarchitectures
• AMD x86 microprocessors
• Computer-related introductions in 2020
• X86 microarchitectures

• Articles with short description
• Short description is different from Wikidata
• Use American English from April 2023
• All Wikipedia articles written in American English
• Use mdy dates from August 2020
• Articles to be expanded from March 2023
• All articles to be expanded
• Articles with empty sections from March 2023
• All articles with empty sections