 A Z80 manufactured in June 1976 | |
| General information | |
|---|---|
| Launched | July 1976 |
| Discontinued | June 2024 |
| Marketed by | Zilog |
| Designed by | Federico Faggin,Masatoshi Shima |
| Common manufacturer | |
| Performance | |
| Max.CPUclock rate | 2.5 MHz to 8 MHz[b] |
| Data width | 8 bits[1] |
| Address width | 16 bits[1] |
| Physical specifications | |
| Transistors |
|
| Packages | |
| Architecture and classification | |
| Application | Embedded, desktop, handheld |
| Technology node | 4 μm process |
| Instruction set | Z80[c] |
| History | |
| Predecessor | Intel 8080 |
| Successors | |
TheZilog Z80 is an8-bit microprocessor designed byZilog, first released in 1976; it played an important role in the evolution of earlypersonal computing. It was designed to besoftware-compatible with theIntel 8080, offering a compelling alternative due to its betterintegration and increased performance. Along with the 8080's sevenregisters and flags register, the Z80 introduced an alternate register set, two 16-bit index registers, and additional instructions, includingbit manipulation and block copy/search.
Originally intended for use inembedded systems like the 8080 was, the Z80's combination of compatibility, affordability, and superior performance led to widespread adoption invideo game systems andhome computers throughout the late 1970s and early 1980s, helping to fuel thepersonal computing revolution. The Z80 was used in iconic products such as theOsborne 1,Radio Shack TRS-80,ColecoVision,ZX Spectrum, Sega'sMaster System and thePac-Man arcade cabinet. In the early 1990s, it was used in portable devices, including theGame Gear and theTI-81 and succeeding graphing calculators.[2][3]
The Z80 was the brainchild ofFederico Faggin, a key figure behind the creation of the Intel 8080. After leaving Intel in 1974, he co-founded Zilog withRalph Ungermann. The Z80 debuted in July 1976, and its success allowed Zilog to establish its ownchip factories.[4] For initial production, Zilog licensed the Z80 to U.S.-basedSynertek andMostek, along with Europeansecond-source manufacturer,SGS. Thedesign was also copied by various Japanese, Eastern European, and Soviet manufacturers gaining global market acceptance as major companies likeNEC,Toshiba,Sharp, andHitachi produced their own versions or compatible clones.
The Z80 continued to be used in embedded systems for many years, despite the introduction of more powerful processors; it remained in production until June 2024, 48 years after its original release. Zilog also continued to enhance the basic design of the Z80 with several successors, including theZ180,Z280, andZ380, with the latest iteration, theeZ80, introduced in 2001 and available for purchase as of 2025[update].[5]
AtFairchild Semiconductor, and later atIntel,physicist andengineerFederico Faggin had been working on fundamentaltransistor andsemiconductor manufacturing technology. He also developed the basic design methodology used for memories andmicroprocessors at Intel and led the work on theIntel 4004, theIntel 8080 and several other ICs.Masatoshi Shima was the principal logic and transistor-level designer of the 4004 and the 8080 under Faggin's supervision, whileRalph Ungermann was in charge of customintegrated circuit design.[6]
In early 1974, Intel viewed microprocessors not so much as products to be sold on their own but as a way to sell more of its main products,static RAM andROM. A reorganization placed some of the formerly independent sections under the direction of Les Vadasz, further diluting the microprocessor's place in the company. That year, the1973–1975 recession reached a peak, and Intel laid off several employees.[6] All of this led to Faggin becoming restless, and he invited Ungermann out for drinks and asked if he would be interested in starting their own company. Ungermann immediately agreed, and as he had less to do at Intel, he left in August or September, followed by Faggin, whose last day at Intel was Halloween 1974.[7] When Shima heard, he asked to come to the new company as well, but having no actual product design or money, they told him to wait.[8]
The newly formed and unnamed company initially began designing a single-chipmicrocontroller called the 2001. They met withSynertek to discuss fabrication on their lines, and when Faggin began to understand the costs involved, it became clear that a low-cost product like this would not be able to compete with a design from a company with its own production lines, like Intel. They then began considering a more complex microprocessor instead, initially known as the Super 80, with the main feature being its use of a +5 V bus[8] instead of the more common −5, +5 and 12 V used by designs like the 8080. The new design was intended to be compatible with the 8080, but add a number of the features of theMotorola 6800, includingindex registers and improvedinterrupts.[9]
While still being set up, the industry newsletterElectronic News heard of them and published a story on the newly formed company. This attracted the attention of Exxon Enterprises,Exxon's high-tech investment arm. At the time, in the midst of the recession, there was littleventure capital available, with a total of $10 million for the entire industry being spent in all of 1975 (equivalent to $60 million in 2025). Someone from Exxon contacted the still-unnamed company,[8] and arranged a meeting that eventually led to them providing an initial $500,000 funding in June 1975 (equivalent to $3 million in 2025).[10]
With funding being discussed and a design to be built,Masatoshi Shima joined in February 1975.[9] Shima immediately set about producing a high-level design, adding several concepts of his own. In particular, he used his experience onNECminicomputers to add the concept of two sets ofprocessor registers so they could quickly respond tointerrupts.[7][d] Ungerman began the development of a series of related controllers and peripheral chips that would complement the design.[11]
Through this period, Shima developed a legendary reputation for being able to convert logic concepts into physical design in realtime; while discussing a proposed feature, he would often interrupt and state how much room that would take on the chip and veto its addition if it was too large.[12] The first pass at the design was complete by April 1975. Shima had completed a logic layout by the beginning of May. A second version of the logic design was issued on August 7 and the bus details by September 16. Tape-out was completed in November and converting the tape into a production mask required two more months.[13]
Faggin had already started looking for a production partner. By this time, Synertek andMostek had both set up the depletion-mode production lines that could be used to produce the design. Having talked to Synertek previously, Faggin approached them first. However, the president of Synertek demanded that the company be given asecond source license, allowing them to sell the design directly. Faggin thought this would mean they could never compete even if they set up their own lines, and the agreement fell through. He then turned to Mostek, who agreed to a term of exclusivity while Zilog got their lines set up, and was eventually given the second source agreement.[14]
After considering multiple names for the new company, and finding them so unmemorable they could not recall them even a day later, Faggin and Ungermann were kicking around ideas based on "integrated logic" when Ungermann said, "How about Zilog?" Faggin immediately agreed, stating they could say it was the "last word in integrated logic". When they met the next day and both immediately recalled it, the company had its name.[15]
The first samples were returned from Mostek on March 9, 1976.[11] By the end of the month, they had also completed anassembler-baseddevelopment system. Some of the Z80 support and peripheral ICs were under development at this point, and some of them were launched during the following year. Among them were the Z80 CTC (counter/timer), Z80 DMA[16] (direct memory access), Z80 DART (dual asynchronous receiver–transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output).
The Z80 was officially launched in July 1976.[17] At the time, concerns existed within the semiconductor industry about the unlicensed reproduction of chip designs by foreign manufacturers. To help deter reverse engineering, the Zilog team incorporated six "traps", transistors that were subtly modified to behave differently than their appearance would suggest. According to Shima, an engineer atNEC later told him that these traps delayed their reverse engineering efforts by six months.[18] NEC later settled a patent infringement dispute with Zilog, securing a license to produce authorized versions of the Z80 and other chips.[19]
Following the successful launch of the Z80, Faggin and Ungermann approached Exxon for funding to establishsemiconductor fabrication plant. Exxon agreed, and Zilog built its own production line, enabling the company to capture an estimated 60 to 70 percent of the total market for Z80 sales.[20] Meanwhile, Mostek was authorized to produce a licensed version of the chip, the MK3880, providing asecond source for customers, a safeguard that Intel lacked. At the time, second-source agreements were considered essential, particularly for startups like Zilog, which carried a higher risk of business failure and supply disruption.[e][9]
Faggin designed theinstruction set to bebinary compatible with the 8080[21][22] so that most 8080 code, notably theCP/Moperating system and Intel'sPL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of themicroarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers andlayout people.[23][24] CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours a week in order to meet the tight schedule given by the financial investors.[4]
The Z80 offered multiple improvements over the 8080:[22]
The Z80 took over from the 8080 and its offspring, the8085, in the processor market[29] and became one of the most popular and widely used 8-bit CPUs.[30][31] Some organizations such asBritish Telecom remained loyal to the 8085 for embedded applications, owing to their familiarity with it and to its on-chip serial interface and interrupt architecture. Likewise,Zenith Data Systems paired the 8085 with the 16-bitIntel 8088 in its first MS-DOS computer, theZenith Z-100, despite having previous experience with its pioneering Z80-basedHeathkit H89 and Zenith Z-89 products. However, other computers were made integrating the Z80 with other CPUs: the Radio ShackTRS-80 Model 16 with aMotorola 68000, theDEC Rainbow with an 8088, and theCommodore 128 with aMOS Technology 8502.
Zilog was later producing a low-power Z80 suitable for the growing laptop computer market of the early 1980s. Intel produced a CMOS 8085 (80C85) used in battery-powered portable computers, such as theKyocera-designed laptop from April 1983, also sold by Tandy (asTRS-80 Model 100), Olivetti, and NEC. In following years, however, CMOS versions of the Z80 (from both Zilog and Japanese manufacturers) would dominate this market as well, in products such as theAmstrad NC100,Cambridge Z88 and Tandy's own WP-2.
Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, at least in markets such asCP/M and other office and home computers. (Most Z80embedded systems usestatic RAM that do not need refresh.) It may also have been its minimalistic two-level interrupt system, or conversely, its general multi-level daisy-chain interrupt system useful in servicing multiple Z80 IO chips. These features allowed systems to be built with less support hardware and simpler circuit board layouts.
However, others claim that its popularity was due to the duplicated registers that allowed fast context switches or more efficient processing of things like floating-point math compared to 8-bit CPUs with fewer registers. (The Z80 can keep several such numbers internally, using HL'HL, DE'DE and BC'BC as 32-bits registers, avoiding having to access them from slower RAM during computation.)[32]
For the originalNMOS design, the specified upper clock-frequency limit increased successively from the introductory 2.5 MHz, via the well known 4 MHz (Z80A), up to 6 MHz (Z80B) and 8 MHz (Z80H).[33][34] An NMOS version was produced as a 10 MHz part beginning in the late 1980s.CMOS versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power standby with internal state retained, having nolower frequency limit.[i] The fully compatible derivativesHD64180/Z180[35][36] andeZ80 are currently specified for up to 33 MHz and 50 MHz, respectively.
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The programming model and register set of the Z80 are fairly conventional, ultimately based on the register structure of theDatapoint 2200. The Z80 was designed as an extension of the Intel 8080, created by the same engineers, which in turn was an extension of the8008. The 8008 was basically aPMOS implementation of the TTL-based CPU of the Datapoint 2200.[j]
The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into a 16-bit address register HL.[k] In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced immediate 16-bit data for BC, DE, HL, and SP loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address.
The Z80orthogonalized this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in the Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. A limitation is that all operand references involving IX or IY require an extra instruction prefix byte, adding at least four clock cycles over the timing of an instruction using HL instead; this sometimes makes using IX or IY less efficient than a method using only the 8080-model registers. The Z80 also introduced a new signedoverflow flag and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions forsigned 16-bit arithmetics.
The 8080-compatible registers AF, BC, DE, HL are duplicated as a separate register file in the Z80,[38] where the processor can quickly (in four t-states, the least possible execution time for any Z80 instruction) switch from one bank to the other;[39] a feature useful for speeding up responses to single-level, high-priority interrupts. The dual register-set is useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code likefloating-point arithmetic or home computer games.
The duplicate register file is often referred to as the "alternate register set" (by some, the "primed" register file since the apostrophe character is used to denote them in assembler source code and the Zilog documentation). This emphasizes that only one set is addressable at any time. However, the 8-bit accumulator A with its flag register F is bifurcated from the "general purpose" register pairs HL, DE and BC. This is accomplished with two separate instructions used to swap their accessibilities:EX AF,AF' exchanges only register pair AF with AF', while theEXX instruction exchanges the three general purpose register pairs HL, DE and BC with their alternates HL', DE' and BC'. Thus the accumulator A can interact independently with any of the general purpose 8-bit registers in the alternate (or primed) register file, or, if HL' contains a pointer to memory, some byte there (DE' and BC' can also transfer 8-bit data between memory and accumulator A).
This can become confusing for programmers because after executingEX AF,AF' orEXX, the contents of the alternate (primed) registers are now in the main registers, and vice versa. The only way for the programmer to understand and track this swapped condition is to trace through the code flow, noting each occurrence of a register swap instruction. Obviously if jump and call instructions are made within these code segments it can quickly become difficult to tell which register file is in context unless carefully commented. Thus it is advisable that exchange instructions be used directly and in short discrete code segments. The Zilog Z280 instruction set includesJAF andJAR instructions which jump to a destination address if the alternate registers are in context (thus officially recognizing this programming complication).
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As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers[40] are:
AF: 8-bitaccumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used forBCD), and an Add/Subtract flag (usually called N) also for BCDBC: 16-bit data/address register or two 8-bit registersDE: 16-bit data/address register or two 8-bit registersHL: 16-bit accumulator/address register or two 8-bit registersSP:stack pointer, 16 bitsPC: program counter, 16 bitsThe new registers introduced with the Z80 are:
IX: 16-bit index or base register for 8-bit immediate offsetsIY: 16-bit index or base register for 8-bit immediate offsetsI: interrupt vector base register, 8 bitsR: DRAM refresh counter, 8 bits (msb does not count)AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF')BC',DE' andHL': alternate (or shadow) registers (toggled in and out with EXX)IFF1 andIFF2, plus the two-bit interrupt mode,IM.Therefresh register,R, increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generatepseudorandom numbers in games, and also in software protection schemes.[41] It has also been employed as a "hardware" counter in some designs; an example of this is theZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt atwrap around (by connecting INT to A6).
Theinterrupt vector register,I, is used for the Z80 specific mode 2 interrupts (selected by theIM 2 instruction). It supplies the high byte of the base address for a 128-entry table ofservice routine addresses which are selected via an index sent to the CPU during aninterrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine.[26] The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-calleddaisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register.
The instructionsLD A,R andLD A,I affect the Z80 flags register, unlike all the otherLD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to the current state of the IFF2 flip-flop.[42]
Although the Z80 is generally considered an eight-bit CPU, it has a four-bitALU, so calculations are done in two steps.[43]
The first Intel 8008assembly language was based on a simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the additional addressing modes in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without beingbinary compatible; however, the 8008 was binary compatible with the Datapoint 2200).
In this process, the mnemonicL, forLOAD, was replaced by various abbreviations of the wordsLOAD,STORE andMOVE, intermixed with other symbolic letters. The mnemonic letterM, formemory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestandingoperand, while registers and combinations of registers became inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on).
| Intel 8008 Datapoint 2200 | Intel 8080 Intel 8085 | Zilog Z80 | Intel 8086/ Intel 8088 |
|---|---|---|---|
| before ca. 1973 | ca. 1974 | 1976 | 1978 |
LBC | MOVB,C | LDB,C | MOVCH,CL |
-- | LDAXB | LDA,(BC) | -- |
LAM | MOVA,M | LDA,(HL) | MOVAL,[BX] |
LBM | MOVB,M | LDB,(HL) | MOVCH,[BX] |
-- | STAXD | LD(DE),A | -- |
LMA | MOVM,A | LD(HL),A | MOV[BX],AL |
LMC | MOVM,C | LD(HL),C | MOV[BX],CL |
LDI56 | MVID,56 | LDD,56 | MOVDL,56 |
LMI56[l] | MVIM,56 | LD(HL),56 | MOVbyteptr[BX],56 |
-- | LDA1234 | LDA,(1234) | MOVAL,[1234] |
-- | STA1234 | LD(1234),A | MOV[1234],AL |
-- | -- | LDB,(IX+56) | MOVCH,[SI+56] |
-- | -- | LD(IX+56),C | MOV[SI+56],CL |
-- | -- | LD(IY+56),78 | MOVbyteptr[DI+56],78 |
-- | LXIB,1234 | LDBC,1234 | MOVCX,1234 |
-- | LXIH,1234 | LDHL,1234 | MOVBX,1234 |
-- | SHLD1234 | LD(1234),HL | MOV[1234],BX |
-- | LHLD1234 | LDHL,(1234) | MOVBX,[1234] |
-- | -- | LDBC,(1234) | MOVCX,[1234] |
-- | -- | LDIX,(1234) | MOVSI,[1234] |
Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.[44] The Z80 syntax uses parentheses around an expression to indicate that the value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address. Note that the 8086 is not a complete superset of the Z80. BX is the only 8086 register pair that can be used as a pointer.
Because Intel claimed a copyright on their assembly mnemonics,[45] a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used:
JP (HL),JP (IX), andJP (IY) which imply an effective address. These load the new PC address from the respective register directly, without indirecting through memory.These principles made it straightforward to find names and forms for all new Z80 instructions, as well asorthogonalizations of old ones, such asLD BC,1234.
There was at least one inconsistency introduced. Even though a subtract with carry is coded asSBC A,r, the non-carry subtract is coded asSUB r rather thanSUB A,r.[46]
Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and8086 syntax are virtuallyisomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language bytranslator programs.[47][48]
The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction" most of which are inherited from the 8080); the four remaining codes are used extensively asopcode prefixes:[49] CB and ED enable extra instructions, and DD or FD select IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080[49] (allowing operation of all 8080 programs on a Z80). The Zilog documentation[50] further groups instructions into the following categories (most from the 8080, others entirely new like the block and bit instructions, and others 8080 instructions with more versatile addressing modes, like the 16-bit loads, I/O, rotates/shifts and relative jumps):
No explicit multiply instructions are available in the original Z80,[51] though registers A and HL can be multiplied by powers of two with ADD A,A and ADD HL,HL instructions (similarly IX and IY also). Shift instructions can also multiply or divide by powers of two.
Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However, the parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a feature lacking in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. (This introduces a subtle incompatibility of the Z80 with code written for the 8080, as the Z80 sometimes indicates signed overflow where the 8080 would indicate parity, possibly causing the logic of some practical 8080 software to fail on the Z80.[m]) This new overflow flag is used for all new Z80-specific 16-bit operations (ADC,SBC) as well as for 8-bit arithmetic operations, while the 16-bit operations inherited from the 8080 (ADD,INC,DEC) do not affect it. Also, bit 1 of the flags register (a spare bit on the 8080) is used as a flag N that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of theDAA instruction (decimal adjust accumulator for BCD arithmetic) checks the N flag and behaves accordingly, so a (hypothetical) subtraction followed later byDAA will yield a different result on an old 8080 than on the Z80. However, this would likely be erroneous code on the 8080, asDAA was defined for addition only on that processor.
The Z80 has six newLD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080.[44] As on the 8080, load instructions do not affect the flags (except for the special-purpose I and R register loads). A result of a regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g.LD A,A). This is effectively aNOP.
New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructionsLDIR andLDDR (load,increment/decrement,repeat) use HL to point to the source address, DE to the destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versionsLDI andLDD move a single byte and bump the pointers and byte counter, which if it becomes zero resets the P/V flag. Corresponding memory-to-I/O instructionsINIR,INDR,OTIR,OTDR,INI,IND,OUTI andOUTD operate similarly, except that B, not BC, is used as the byte counter.[52][53] The Z80 can input and output any register to an I/O port using register C to designate the port. (The 8080 only performs I/O through the accumulator A, using a direct port address specified in the instruction; a self-modifying code technique is required to use a variable 8080 port address.)
The last group of block instructions perform aCP compare operation between the byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versionsCPIR andCPDR only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after (CPIR) or before (CPDR) the matching byte. If no match is found, the Z flag is reset. There are non-repeating versionsCPI andCPD.
Unlike the 8080, the Z80 can jump to a relative address (JR instead ofJP) using a shorter instruction with a signed 8-bit displacement. There are unconditional and conditional forms of this instruction. Only the zero and carry conditions can be tested. (All 8080 jumps and calls, conditional or not, are three-byte instructions.) If jump is taken, the two-byteJR instructions are slower than the 8080-style three-byteJP instructions; if not taken,JR instructions are quicker.
A two-byte instruction specialized for program looping is also new to the Z80:DJNZ (decrementjump ifnon-zero) takes a signed 8-bit displacement as an operand. The B register is decremented, and if the result is nonzero, then program execution jumps relative to PC; the flags remain unaltered. To perform an equivalent loop on an 8080 requires separateDEC and conditional jump (to a two-byte absolute address) instructions (totalling four bytes), and theDEC alters the flag register.
The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such asrecords) or at fixed offsets relative a variable base address (as inrecursivestack frames) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g., 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL andINC to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the "main" registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80 (being 1 clock slower than in the 8080/8085); nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different offset displacement bytes (which were typically calculated dynamically) into indexed instructions; this is an example ofself-modifying code, which was regular practice on nearly all early 8-bit processors with non-pipelined execution units.
The index registers have a parallel instruction toJP (HL), which isJP (IX) andJP (IY). This is often seen in stack-oriented languages likeForth, which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears hundreds of times in an application, and usingJP (IX) rather thanJP THREAD saves a byte and two T-states for each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency.
The 10-year-newer microcodedZ180 design could initially afford more "chip area", permitting a slightly more efficient implementation (using a widerALU, among other things); similar things can be said for theZ800,Z280, andZ380. However, it was not until the fully pipelinedeZ80 was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.[citation needed]
The index registers, IX and IY, were intended as flexible 16-bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality they were implemented as a pair of 8-bit registers,[54] in the same fashion as the HL register, which is accessible either as 16 bits or separately as theHigh andLow registers. The binary opcodes (machine language) were identical, but preceded by a new opcode prefix.[55] Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. For example, the opcode 26h followed by an immediate byte value(LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar toLD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction;[55] in this case the DD prefix is only applied to the (IX+d) portion of the instruction. The halves of the XY registers could also hold operands for 8-bit arithmetic, logical and compare instructions, sparing the regular 8-bit registers for other use. The undocumented ability to increment and decrement the upper half of an index register made it easy to expand the range of the normal indexed instructions, without having to resort to the documentedADD/SBC XY,DE orADD/SBC XY,BC.
There are several other undocumented instructions as well.[56] Undocumented orillegal opcodes are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed (or especially likely) to work the same way for every undocumented opcode.
TheOTDR instruction does not conform to the Z80 documentation. Both theOTDR andOTIR instructions are supposed to leave the carry (C) flag unmodified. TheOTIR instruction operates correctly; however, during the execution of theOTDR instruction, the carry flag takes the results of a spurious compare between the accumulator (A) and the last output of theOTDR instruction.[57]
The following Z80 assembly source code is for a subroutine namedmemcpy that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. It demonstrates a variety of instructions but in practice it would not be coded this way as the Z80 has a single instruction that will replace this entire subroutine:LDIR. The sample code will move one byte every 46 T-states. Substituting theLDIR instruction will move each byte in only 21 T-states. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs.
1000 1000 1000 F5 1001 7E 1002 12 1003 23 1004 13 1005 0B 1006 78 1007 B1 1008 C2 01 10 100B F1 100C C9 100D | ; memcpy --; Copy a block of memory from one location to another.; This routine is the equivalent of LDIR;; Entry registers; HL - Address of source data block; DE - Address of destination data block; BC - Number of bytes to copy;; Return registers; HL - First byte after source data block; DE - First byte after destination data block; BC - Zero; (LDIR does not fully save AF. H, P/V, and N are reset.)org1000h; Origin at 1000hmemcpypublicpushaf; Save AF like LDIRlooplda,(hl); Copy 1 source byteld(de),a; to its destinationinchl; Bump source pointerincde; Bump dest pointerdecbc; Count the copied bytelda,b; Test BC for zeroorc; If BC != 0,jpnz,loop; repeat the looppopaf; Restore AFret; Returnend |
Each instruction is executed in steps that are usually termedmachine cycles (M-cycles), each of which can take between three and six clock periods (T-states).[58] Each M-cycle corresponds roughly to one memory access or internal operation. Multiple instructions actually end during the M1 of thenext instruction which is known as afetch/execute overlap.
| Total M-cycles | T-states | instruction | M1 | M2 | M3 | M4 | M5 | M6 |
|---|---|---|---|---|---|---|---|---|
| 1[59] | 4[1] | INCB | opcode | |||||
| 2[60] | 7 | ADDA,n | opcode | n | ||||
| 3[61] | 11 | ADDHL,DE | opcode | internal | internal | |||
| 4[62] | 15 | SETb,(HL) | prefix | opcode | R(HL), set | W(HL) | ||
| 5[63] | 19 | LD(IX+d),n | prefix | opcode | d | n,add | W(IX+d) | |
| 6[64] | 23 | INC(IY+d) | prefix | opcode | d | add | R(IY+d),inc | W(IY+d) |
The Z80 machine cycles are sequenced by an internalstate machine which builds each M-cycle out of 3, 4, 5 or 6 T-states depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements onmemory access times, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.[citation needed]
One central example of this is that, foropcode fetch, the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the6800,6502, or similar, where this period would typically last typically 30-40% of a clock cycle.[citation needed] With memory chip affordability (i.e. access times around 450-250 ns in the 1980s[citation needed]) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.
Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regardingSRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.
The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus.[65]
Zilog introduced a number of peripheral parts for the Z80, which all support the Z80's interrupt handling system and I/O address space. These include the counter/timer channel (CTC),[66] the SIO (serial input/output), the DMA (direct memory access), the PIO (parallel input/output) and the DART (dual asynchronous receiver–transmitter). As the product line developed, low-power, high-speed andCMOS versions of these chips were introduced.
Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 has a separate control line and address space for I/O instructions. While some Z80-based computers such as theOsborne 1 used "Motorola-style"memory mapped input/output devices, usually the I/O space was used to address one of the Zilog peripheral chips compatible with the Z80. During the timing for an I/O read or an I/O write operation, a single wait cycle is automatically inserted by the Z80.[67] Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.
The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16-bit BC register on the address bus;[57] OUT (n),A and IN A,(n) places the contents of the A register on b8–b15 of the address bus and the port addressn on b0–b7 of the address bus. A designer could choose to decode the entire 16-bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in theAmstrad CPC/PCW andZX81.
Mostek, which produced the first Z80 for Zilog, offered itsecond-source as MK3880. SGS-Thomson (nowSTMicroelectronics) was a second source, too, with their Z8400. Sharp andNEC developed second sources for the NMOS Z80, the LH0080 and μPD780C, respectively. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, includingSonyMSX computers, and a number of computers in theSharp MZ series.[68] Sharp developed the LH0080A and LH0080B to operate at frequencies of 4 MHz and 6 MHz, respectively.[69] Sharp also developed LH0083[70] compatible with Z80 DMA.
Toshiba made a CMOS-version, the TMPZ84C00, which is believed[by whom?] (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z8400, Z80-chips made byGoldStar (nowLG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) inNMOS andCMOS made byROHM Electronics. The LH5080,[71] LH5081,[72] and LH5082,[73] which are CMOS versions of the Z80, PIO, and CTC respectively, are manufactured by Sharp.
InEast Germany, an unlicensed clone of the Z80, known as theU880, was manufactured. It was used extensively inRobotron's and VEB Mikroelektronik Mühlhausen's computer systems (such as theKC85-series) and also in multiple self-made computer systems. InRomania another unlicensed clone could be found, namedMMN80CPU and produced byMicroelectronica, used in home computers like TIM-S, HC, COBRA.
Also, several clones of Z80 were created in theSoviet Union, notable ones being theT34BM1, also calledКР1858ВМ1 (parallelling the Soviet 8080-cloneKR580VM80A). The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are more T34BM1s than КР1858ВМ1s.[citation needed]
During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with theCP/M operating system, a combination that dominated the market at the time.[89][90] Four well-known examples of Z80 business computers running CP/M are theHeathkit H89, the portableOsborne 1, theKaypro series, and theEpson QX-10. Less well-known was the expensive high-endOtrona Attache.[91] Some systems used multi-tasking operating system software (likeMP/M orMorrow's Micronix) to share the one processor between severalconcurrent users.
Multiple home computers were introduced that used the Z80 as the main processor or as a plug-in option to allow access to software written for the Z80. Notable are theTRS-80 series, including the original model (later retronymed "Model I"),Model II,Model III, andModel 4, which were equipped with a Z80 as their main processor, and some (but not all) other TRS-80 models which used the Z80 as either the main or a secondary processor. Other notable machines were theDECRainbow 100, and theSeequa Chameleon, both of which featured both anIntel 8088 and a Z80 CPU, to support either 8-bit CP/M-80 applications running on the Z80, or a custom MS-DOS that was not fully compatible withPC DOS applications running on the 8088.
In 1981, Multitech (later to becomeAcer) introduced theMicroprofessor I, a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited inSouthampton, England.
In 1984 Toshiba introduced the Toshiba MSX HX-10 in Japan and Australia.
In 1985,Sharp introduced theHotbit andGradiente introduced theExpert, which became the dominant 8-bit home computers inBrazil until the late 1980s.
Use of the Z80 in lighter, battery-operated devices became more widespread with the availability of CMOS versions of the processor. It also inspired the development of other CMOS based processors, such as the LH5801[92] from Sharp. TheSharp PC-1500, aBASIC-programmablepocket computer was released in 1981, followed by the improvedSharp PC-1600 in 1986 and theSharp PC-E220 in 1991. Later models of theSharp Wizard series of personal organizers also were Z80 based.Laptops which could run the CP/M operating system just like the desktop machines followed withEpson PX-8 Geneva in 1984, and in 1985 theEpson PX-4 andBondwell-2. While the laptop market in subsequent years moved to more powerfulIntel 8086 processors and the MS-DOS operating system, light-weight Z80-based systems with a longer battery life were still being introduced, such as theCambridge Z88 in 1988 and theAmstrad NC100 in 1992. The Z80-derivedZ8S180 also found its way into an earlypen-operatedpersonal digital assistant, theAmstrad PenPad PDA600 in 1993. Hong Kong-basedVTech produced a line of small laptop computers called "Lasers" based on a Z80.[93][94] The last two were the Laser PC5[95] and PC6.[96]TheCidco MailStation Mivo 100, first released in 1999, was a stand-alone portable email device, with a Z80-based microcontroller.[97] Texas Instruments produced a line of pocket organizers (ending in 2000) using Toshiba processors built around a Z80 core; the first of these was the TI PS-6200[98] and after a lengthy production run of some dozen models culminated in their PocketMate series.[99]
The Zilog Z80 has long been a popular microprocessor inembedded systems andmicrocontroller cores,[40] where it remains in widespread use today.[30][100] Applications of the Z80 include uses inconsumer electronics, industrial products, and electronic musical instruments. For example, Z80 was used in the groundbreaking music synthesizerProphet-5,[101] as well as in the firstMIDI-equipped synthesizer, theProphet 600.[102] The Z80 was the basis for allE-mu Systems instruments from 1976 to 1986.[103]Casio used the Z80A in itsPV-1000 video game console.
Many early-1980s arcade video games, including the arcade gamePac-Man, contain Z80 CPUs.
The Z80 was used in Sega'sMaster System andGame Gear consoles. TheSega Genesis contains a Z80, with its own 8 KB of RAM, which runs in parallel with the MC68000 main CPU, has direct access to the system's sound chips and I/O (controller) ports, and has a switched data path to the main memory bus of the 68000 (providing access to the 64 KB main RAM, the software cartridge, and the whole video chip); in addition to providing backward compatibility with Master System games, the Z80 is often used to control and play back audio in Genesis software.[n]
Z80 CPUs were also used in the popularTI-8x series of graphing calculators fromTexas Instruments, beginning in 1990 with theTI-81, which features a Z80 clocked at 2 MHz. Most higher-line calculators in the series, starting with theTI-82 andTI-85, clock their Z80 CPUs at 6 MHz or higher. (A few models with TI-8x names use other CPUs, such as the M68000, but the vast majority are Z80-based. On those, it is possible to run assembled or compiled user programs in the form of Z80 machine-language code.)
TI-83 andTI-84 Plus model graphing calculators uses the Z80 while theTI-84 Plus CE series use theeZ80; all three calculator series are still sold by Texas Instruments as of 2025.
In the late 1980s, a series ofSoviet landline phones called "AON" featured the Z80; these phones expanded the feature set of the landline withcaller ID, differentringtones based on the caller,speed dial and so forth.[104] In the second half of the 1990s however, manufacturers of these phones switched to 8051 compatible MCUs to reduce power consumption, and prevent compact wall power adapters from overheating.
On April 15, 2024, Zilog announced the discontinuation of the Z80 processor, with orders being accepted until June 14, 2024. The announcement included 13 variants of the Z80 processor, some of which wereDIP40 variants of the chip. Zilog will continue to manufacture the upgradedeZ80 version of the processor.[5]
ADDing zero to it, bySUBtracting zero from it, or byORing orXORing it with zero; all of these are single-instruction operations of the same speed and size, on both the 8080 and the Z80. If the programmer happened to choose to test parity byORing orXORing with zero, then the Z80 will execute the program correctly, but if the programmer chose to test parity byADDing orSUBtracting zero, then the Z80 will always reset the P/V flag (since adding or subtracting zero never causes an overflow or underflow) instead of assigning P to correctly indicate the parity of the byte—as the 8080 or 8085 would—and the program may fail. Nothing in the Intel 8080 programming manuals discouraged use of arithmetic instructions, or prescribed using logical instructions, to test parity, so there is little reason that an 8080 programmer should select one over the other. In real applications, it is unlikely that arithmetic instructions given in this example would be selected to test parity as logical instructionsAND A andOR A are faster and one byte shorter.interrupt processing commences according to the interrupt method stipulated by the IM i,i = 0, 1, or 2, instruction. Ifi = 1, for direct method, the PC is loaded with 0038H. Ifi = 0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte. Ifi = 2, for indirect vector method, the interrupting device must then place a byte. The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte.
The register architecture of the Z80 is more innovative than that of the 8085
In the 8-bit world, the two most popular microcomputers are the Z80 and 6502 computer chips.
In addition to supporting the entire Z80 instruction set, the Z180
The designers picked an architecture compatible with the Z80, giving Z80 users a completely software compatible upgrade path. The 64180 processor runs every Z80 instruction exactly as a Z80 does
All mnemonics copyright Intel Corporation 1977
[...] The8086 is software-compatible with the8080 at the assembly-language level. [...]
[...] AnIntel translator program could convert8080 assembler programs into8086 assembler programs [...]
It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, accesses an additional 308 instructions.
The 8-bit microprocessors that preceded the 80x86 family (such as the Intel 8080, the Zilog Z80, and the Motorola) did not include multiplication.
Undocumented Z80 codes allow 8 bit operations with IX and IY registers.
If an opcode works with the registers HL, H or L then if that opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY, IYH, IYL), with some exceptions. The exceptions are instructions like LD H,IXH and LD L,IYH.
The I/O instructions use the whole of the address bus, not just the lower 8 bits. So in fact, you can have 65536 I/O ports in a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the I/O block instructions put the whole of BC on the address bus. IN A,(n) and OUT (n),A put A*256+n on the address bus.
ADD A, n Add accumulator with immediate data n. MEMORY Timing: 2 M cycles; 7 T states.
Most MZ's use the 8bit CPU LH0080 / Z80 [...]
The 64180 is a Hitachi-supplied Z80 core with numerous on-chip "extras". Zilog's version is the Z180, which is essentially the same part.
Both Toshiba and Zilog sell the 84013 and 84015, which are Z80 cores with conventional Z80 peripherals integrated on-board.
Kawasaki's KL5C80A12, KL5C80A16 and KL5C8400 are high speed 8-bitMCUs and CPU. Their CPU code, KC80 is compatible with Zilog's Z80 at binary level. KC80 executes instructions about four times faster than Z80 at the same clock rate
Rabbit Semiconductor's Rabbit 3000 microprocessor, which is a much improved and enhanced derivative of ZiLOG, Inc.'s venerable Z80 microprocessor.
The Rabbit parts are based closely on the Zilog Z180 architecture, although they are not binary compatible with the Zilog parts.
and CP/M continued to dominate the 8-bit world of microcomputers.
The idea of a generic operating system is still in its infancy. In many ways it begins with CP/M and the mishmash of early 8080 and Z80 computers.
Sources
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