| Created by | Silicore Corporation |
|---|---|
| Width in bits | 8, 16, 32, 64 |
| Style | Parallel |
| Hotplugging interface | No (On chip bus) |
| External interface | No |
TheWishbone Bus is anopen source hardwarecomputer bus intended to let the parts of anintegrated circuit communicate with each other. The aim is to allow the connection of differingcores to each other inside of a chip. TheWishbone Bus is used by many designs in theOpenCores project.
Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.
This ambiguity is intentional. Wishbone is made to let designers combine several designs written inVerilog,VHDL or some other logic-description language forelectronic design automation (EDA). Wishbone provides a standard way for designers to combine thesehardware logic designs (called "cores").Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generatedcombinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.
Wishbone isopen source. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples ofprior art, to prove its concepts are in the public domain.
A device does notconform to the Wishbone specification unless it includes adata sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.
TheSimple Bus Architecture is a simplified version of the Wishbone specification.[1]
Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such ascrossbar switches. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.[2][3]
 | This sectionneeds additional citations forverification. Relevant discussion may be found on thetalk page. Please helpimprove this article byadding citations to reliable sources in this section. Unsourced material may be challenged and removed.(June 2025) (Learn how and when to remove this message) |
Wishbone control signals are compared to other system on a chip (SoC) bus standards in the below table:[4]
| Wishbone | Avalon Bus | Description |
|---|---|---|
| cyc | = !write_n or !read_n | indicates that a valid bus cycle is in progress |
| stb | = chipselect | indicates a valid data transfer cycle |
| we | = !write_n and read_n | indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles. |
| ack | = !waitrequest | indicates the termination of a normal bus cycle by slave device. |
| Avalon Bus | Wishbone | Description |
|---|---|---|
| chipselect | = stb | indicates that slave device is selected. |
| write_n | = !(cyc and we) | indicated that master requests to write to slave device. |
| read_n | = !(cyc and !we) | indicated that master requests to read from slave device. |
| waitrequest | = !ack | indicates that slave requests that master wait. |
| General | |
|---|---|
| Standards |
|
| Storage |
|
| Peripheral | |
| Audio | |
| Portable | |
| Embedded | |
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |