TheVEX prefix (from "vector extensions") andVEX coding scheme are an extension to thex86-64instruction set architecture formicroprocessors fromIntel,AMD and others. It was introduced with theAVX instruction set.

The VEX prefix consists of three bytes and can be added to new and existing instructions. It is a superset of theREX prefix and provides 16 bits of payload in total. The VEX prefix can also be encoded into a shorter two-byte variant, if the omitted bits have specific values.

The VEX coding scheme allows the definition of new instructions and the extension or modification of previously existinginstruction codes. This serves the following purposes:

• Theopcode map is extended to make space for future instructions.
• It allows instruction codes to have up to four operands (plus immediate), where the original scheme allows only two operands (plus immediate).
• It allows the size ofSIMDvectorregisters to be extended from the 128-bit XMM registers to the 256-bit YMM registers. There is room for further extensions of the register size.
• It allows existing two-operand instructions to be modified into non-destructive three-operand forms where the destination register is different from both source registers. For example,c ←a +b instead ofa ←a +b (where registera is changed by the instruction).

The VEX prefixreplaces the most commonly used instruction prefix bytes and escape bytes. In many cases, the number of prefix bytes and escape bytes that are replaced is the same as the number of bytes in the VEX prefix, so that the total length of the VEX-encoded instruction is the same as the length of the legacy instruction code. In other cases, the VEX-encoded version is longer or shorter than the legacy code. In 32-bit mode VEX encoded instructions can only access the first 8 YMM/XMM registers; the encodings for the other registers would be interpreted as the legacy LDS and LES instructions that are not supported in 64-bit mode.

While it is required for 256-bitAVX operations, the VEX prefix simply provides an alternative encoding for 128-bit SSE operations. For the most part, the operation is identical no matter which encoding is used. There is, however, one major difference:

When a VEX prefix is used, the high bits of the destination register are cleared (zeroed), while SSE operations without VEX leave the high bits of destination SIMD registers unmodified.

This does not affect the computation itself, but does affect any required save and restore operations. In particular, a called function written without knowledge of AVX or VEX may save acallee-saved register, use the register, and restore its value, using 128-bit operations, all without disturbing the more-significant bits.

This merging of unmodified and newly-computed portions of a register is difficult for the (now-ubiquitous) optimization ofregister renaming, as the unchanged portions of the destination register must be copied to the renamed destination register. x86 processors use special techniques to optimize this (such as thevzeroupper instruction), but it still comes at a performance penalty.^[1]

The VEX coding scheme uses aopcode prefix consisting of two or threebytes, which may be added to existing or new instruction codes.^[2]

Two instructions (that were previously defined as invalid opcodes in 64-bit mode) were repurposed as the leading byte of the new VEX prefixes:0xC4 for the three-byte variant and0xC5 for the two-byte variant.

The VEX prefix replaces the0x66,0xF2 and0xF3 opcode prefixes, the REX prefix, and the0x0F,0x0F 0x38 or0x0F 0x3A opcode prefixes. It maynot be used with one-byte opcodes which do not begin with0x0F, nor with the LOCK (0xF0) prefix. It may be preceded only by address size (0x67) or segment (0x26,0x2E,0x36,0x3E,0x64,0x65) prefixes.

In the x86 architecture, instructions with a memory operand almost always use theModR/M byte which specifies theaddressing mode. This byte has three bit fields:

• mod, bits [7:6] - combined with ther/m field, encodes either 8 registers or 24 addressing modes. Also encodes opcode information for some instructions.
• reg/opcode, bits [5:3] - depending on primary opcode byte, specifies either a register or three more bits of opcode information.
• r/m, bits [2:0] - can specify a register as an operand, or combine with themod field to encode an addressing mode.

The base-plus-index and scale-plus-index forms of 32-bit addressing (encoded with r/m = 100 and mod ≠ 11) require another addressing byte, the SIB byte. It has the following fields:

• scale factor, encoded with bits [7:6]
• index register, bits [5:3]
• base register, bits [2:0].

TheVEX3 prefix contains all bit-fields from the REX prefix as well as various other prefixes, expanding addressing mode, register enumeration, operand size and width:

• R̅, X̅ and B̅ bits are complements of the REX prefix's R, X and B bits; these provide a fourth (high) bit for register index fields (ModRM reg, SIB index, and ModRM r/m; SIB base; or opcode reg fields, respectively) allowing access to 16 instead of 8 registers.
• One W bit, equivalent to the REX prefix's W bit, specifies a 64-bit operand; for non-integer instructions, it is a general opcode extension bit.
• Four v̅ bits are the complement of an additional source register index.
• One L bit indicates the vector length; 0 for 128-bit SSE (XMM) registers, and 1 for 256-bit AVX (YMM) registers.
• Two p bits encode additional prefix bytes. The values 0, 1, 2, and 3 correspond to implied no, 0x66, 0xF3, and 0xF2 prefixes. These encode the operand type for SSE floating-point instructions: packed single, packed double, scalar single and scalar double, respectively.
• Fivem bits are used to specifyopcode map to use. Of the 32 possible opcode maps that can be encoded withm₄m₃m₂m₁m₀ , opcode maps 1, 2 and 3 are used to provide compact replacements for legacy 2-byte and 3-byte opcodes - these three opcode maps are equivalent to leading escape byte sequences0x0F,0x0F 0x38 and0x0F 0x3A, respectively. The other VEX opcode maps have seen little use - as of December 2023, the only known uses of other maps are map 0 for theXeon Phi-specificJKZD/JKNZD instructions^[3] and map 7 for the plannedURDMSR/UWRMSR instructions.^[4] Maps 4/5/6 are used with theEVEX prefix, but none of the instructions in those maps are VEX-encodable.

TheVEX2 prefix is a 2-byte abbreviation of the VEX3 prefix, which may be used when the omitted fields have the following values:

• W = 0: 32-bit operand size
• B̅ = 1 (B = 0): Base register is among the first 8
• X̅ = 1 (X = 0): Index register (if a SIB byte is present) is among the first 8
• m = 00001: 2-byte opcode beginning with 0x0F

Instructions which require different values for these fields must be encoded with the VEX3 prefix. VEX2 does include an R̅ bit, an L bit, two p bits, and an additional 4-bit source register (v), so is useful for many SSE and AVX instructions as long as the register/memory operand uses only the first 8 registers.

Instructions coded with the VEX prefix can have up to four variable operands (in registers or memory) and one constant operand (immediate value). Instructions that need more than three variable operands use immediate operand bits to specify a 4th register operand (IS4 above). At most one of the operands can be a memory operand; and at most one of the operands can be an immediate constant of 4 or 8 bits. The remaining operands are registers.

TheAVX instruction set is the first instruction set extension to use the VEX coding scheme. The AVX instruction set uses the VEX prefix only for instructions using theSIMD XMM registers.

However, the VEX coding scheme has been used for other instruction types as well in subsequent expansions of the instruction set. For example:

• BMI introduced VEX-coded arithmetic andbit manipulation instructions that operate on general purpose registers.
• AVX-512 introduced 8 mask registers and added VEX-coded instructions to manipulate them. (VEX.B̅ is ignored when the field is used to encode a mask register, but VEX.R̅ and VEX.v̅₃ are not, and must be set to 1 in 64-bit mode.^[5])
• AMX introduced 8 tile registers and added VEX-coded instructions to manipulate them.

The VEX prefix's initial-byte values, 0xC4 and 0xC5, are the same as the opcodes of the LDS and LES instructions. Not supported in 64-bit mode, the ambiguity is resolved in 32-bit mode by exploiting the fact that a legal LDS or LES'sModR/M byte cannot specify a register source operand; i.e., be of the form11xxxxxx. Various bit-fields in the VEX prefix's second byte are inverted to ensure that the byte is always of this form.

Legacy SIMD instructions with a VEX prefix added are equivalent to the same instructions without VEX prefix with the following differences:

• The VEX-encoded instruction can have one more operand, making it non-destructive.
• A 128-bit XMM instruction without VEX prefix leaves the upper half of the full 256-bit YMM register unchanged, while the VEX-encoded version sets the upper half to zero.
• 128-bit XMM instructions without VEX prefix usually require any memory arguments to be16-byte aligned - VEX-encoded versions allow misaligned memory operands.

Instructions that use the whole 256-bit YMM register should not be mixed with non-VEX instructions that leave the upper half of the register unchanged, for reasons of efficiency.^[6][7]

The VEX prefix is not supported inreal mode and virtual-8086 mode (all instructions with the VEX prefix will cause #UD in these modes).

• In August 2007,AMD proposed theSSE5 instruction set extension which includes a new coding scheme for instructions with three operands, using an extra byte named DREX, and intended for theBulldozer processor core in 2011.^[8][9] However, in 2009, SSE5 was canceled and never implemented.
• In March 2008, Intel proposed theAVX instruction set, using the new VEX coding scheme.^[10]
• In August 2008, commentators deplored the expected incompatibility between AMD and Intel instruction sets, and proposed that AMD revise their plans and replace the DREX scheme with the more flexible and extensible VEX scheme.^[11]
• In May 2009, AMD announced a revision of the proposed SSE5 instruction set to make it compatible with the AVX instruction set and the VEX coding scheme. The revised SSE5 is calledXOP.^[12]
• 2011. The AVX instruction set is supported in Intel'sSandy Bridge microprocessor architecture, while theAVX,XOP andFMA4 instruction sets are supported in the AMDBulldozer processor.^[13]
• The VEX-encodedFMA3 instruction set ships with AMDPiledriver processors (in 2012) and IntelHaswell processors (in 2013).
• In July 2023, Intel announcedAdvanced Performance Extensions (APX) which extended the EVEX prefix and introduced the REX2 prefix.

• REX prefix
• EVEX prefix

• X86 instructions
• SIMD computing

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