 | |
| General information | |
|---|---|
| Launched | 1994; 31 years ago (1994) |
| Discontinued | current |
| Common manufacturer |
|
| Performance | |
| Max.CPUclock rate | 32 kHz to 320 MHz |
| Data width | 32 |
| Address width | 32 |
| Cache | |
| L1cache | configurable |
| Architecture and classification | |
| Application | Embedded, Mobile equipment, Air conditioner, Automotive |
| Technology node | 0.8 μm to 40 nm |
| Microarchitecture | V810 (1991), V850 (1994), V850E (1996), V850E1 (1999), V850ES (2002), V850E2 (2004), V850E1F (2005), V850E2v2 (FIX ME), V850E2v3 (2009), V850E2v4 (2010), V850E2v3S (2011), V850E3v5 (2014) |
| Instruction set | V800 Series |
| Extensions |
|
| Number of instructions | v850: 74 v850e: 81 v850e1: 80 (83) v850e1f: 96 v850e2: 89 v850e2v3: 98 V850e3v5:FIX ME |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code names |
|
| Variant |
|
| History | |
| Predecessor | "V80" CISC core |
V850 is a 32-bitRISCCPU architecture produced byRenesas Electronics forembeddedmicrocontrollers. It was designed byNEC as a replacement for their earlierNEC V60 family, and was introduced shortly before NEC sold their designs to Renesas in the early 1990s. It has continued to be developed by Renesas as of 2018[update].
The V850 architecture is aload/store architecture with 32 32-bitgeneral-purpose registers. It features acompressed instruction set with the most frequently used instructions mapped onto 16-bit half-words.
Intended for use in ultra-lowpower consumption systems, such as those using 0.5 mW/MIPS, the V850 has been widely used in a variety of applications, includingoptical disk drives,hard disk drives,mobile phones,car audio, andinverter compressors forair conditioners. Today, microarchitectures primarily focus on high performance and high reliability, such as thedual-lockstepredundant mechanism for theautomotive industry; and the V850 and RH850 families are comprehensively used in cars.
The V850/RH850 microcontrollers are also used prominently on non-Japanese automobile marques such as Chevrolet, Chrysler, Dodge, Ford, Hyundai, Jeep, Kia, Opel, Range Rover, Renault and Volkswagen Group brands.
The V850 is thetrademark name for a 32-bitRISCCPU architecture forembeddedmicrocontrollers ofRenesas Electronics Corporation. It was originally developed and manufactured byNEC Corporation in the early 1990s[1][2](thecopyright mark for themicrocode on thepackage shows 1991) as a branch of the V800 Series[3]: 97, PDF103 and is still being evolved today.[4]
Its base-architecture has been succeeded by the V850 family variants, named V850E, V850E1, V850ES,[5]V850E1F, V850E2, V850E2M, V850E2S, and the RH850 family (V850E2M, V850E2S, and V850E3) CPU cores.
Many compilers and debuggers are available from variousdevelopment tool vendors.
Real-time operating systems are provided by compiler vendors.
In-circuit emulators (ICE) are provided by many vendors. Legacy proven pod-based types—theJTAG-based N-Wire interface with the N-trace type, and the Nexus interface with the Aurora Trace type—are available.
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The first V850 CPU core was used in manyDVD drives manufactured by NEC's and Sony'sOptiarc (later wholly owned by Sony).[6][7]NEC Electronics(currentlyRenesas Electronics) itself intensively developedapplication-specific standard products (ASSPs) forSCOMBO Seriesoptical disk drives.[8][9]This first generation of processor core was also used forhard disk drives manufactured byQuantum Corporation (see photo).
In 1997, the V850/xxn product line started with the V850/SA1[10]and the V850/SV1[11]and expanded its application to ultra-low-power products such as "handycamcorders."It has a main and sub internaloscillatoramplifier working from 1.8 V to 3.6 V with externalcrystal orceramicresonator.[10]Software STOP mode, whose internal watch timer operates with a 32.768 kHz sub-oscillator, typically consumes only 8μA ofelectrical current.[12][13]In 1998, NEC launched the V850/SB1[14]withIEBus controller, for car audio, an ultra-low-power (3.6 mW@5V/MIPS) and ultra-low-noise (EMI/EMS) 5V product.[15]The V850/SC1[16]was also for car audio.[17]These strategic product line expansions succeeded in increasing the number of devices sold.
The first generation of the V850 core is also used for some NEC mobile phones.[18]It is also used for the programmable-host CPUs of some small form factorGSM/GPRS mobile devices withGPS embeddedmodem modules.[19]
In the next phase, NEC targeted theautomotive industry with aCAN bus controller based on the V850[20]as the V850/SF1.[21]Later on, the automotive industry became the main target of the V850 and RH850.
The V850E core was targeted atsystem-on-a-chip (SoC) applications as well as standard products,[22][23]and was used for some Japanese domesticmobile phones, includingSony Mobile's and NEC's.[24][25][26][27][28]V850E and V850ES are also used inair conditioninginverter compressors.[29][30][31][32]At this stage, another mass market was its use in car audio.[33]The V850ES core succeeded in the low-power embedded-product line,[34]and isISA-compatible with the V850E.NEC Electronics (currently, Renesas Electronics) adopted the V850 CPU core for its USB 3.0 controllers.[35]: 11
Around 2005, several companies started afeasibility study for theFlexRay controller on the V850E platform. Yokogawa Digital Computer (currently DTS INSIGHT) developed an evaluation board named GT200 with a V850E/IA1 and afield-programmable gate array (FPGA), which employs the FlexRay controller developed byBosch.[36]: 78, PDF80
The V850E2 core primarily targeted automotive areas,[37]but was also used for NEC's mobile phones.[38]
The V850 family lineup (based on V850E, V850ES, and V850E2 cores) and the Renesas RH850 family (based on the V850E3 core, as of 2018) are mainly employed in automotive applications as well as inter-equipment connectivity and motor-control specificmicrocontroller units (MCUs).[39][40]
The V850 is aunregistered trademark but not aregistered one.[41]NEC once applied for a trademark to be registered with theJapan Patent Office, but it was rejected,[42][43]as it was a natural extension of the series number.However, this action has been enough to prevent other people or organizations from registering it as a trademark. In addition, Renesas has been using the V850X/xxn type trademark, such as V850E/MA1, for more than 20 years, because the combination of one alphabetical with two numerical characters cannot be granted as a registered trademark. It is thus free to use without registration.
One exception is V850E/PHO3 (PHOENIX 3, or PHOENIX-FS).[44]: 3 [45]: 33 Another usage of PHOENIX 3 by Renesas Electronics is the COOL PHOENIX 3, which employs the ARM Cortex-M0 core.[46]PHOENIX 3 is a registered trademark ofthe 3DO Company asUSPTO Reg. 2,009,119.[47]
According to current Renesas Electronics documentation, at least the following strings are regarded as its trademark: "V800 Series", "V850 family", "V850/SA1", "V850/SB1", "V850/SB2", "V850/SF1", "V850/SV1", "V850E/MA1", "V850E/MA2", "V850E/IA1", "V850E/IA2", "V850E/MS1", "V850E/MS2", "V851", "V852", "V853", "V854", "V850", "V850E", and "V850ES".[41][48]
Because the V850 trademark has been used for more than 20 years, most people do not know that the RH850 family is based on an extension of the V850 instruction set architecture, and has backward compatibility with V850, V850E, V850ES, and V850E2. The RH850 is consequently thought of as being without the legacy software compatibility of the V850.[49][50]
Because the V850 family[48]: 16 was developed as a branch of the V800 series,[3]: 97, PDF103 the basic CPU architecture is inherited from the V810.[52]The instruction set architecture of the first V850 is drastically modified from that of the V810, but the difference is within a patch level from the GNU Compiler Collection point of view.[53] The main purpose of this change is to implement saturation arithmetic at customers' request.
The detailed design methodology of the V810 is described in this journal.[56]The V850 utilizes these design assets; but thedatapath logic was changed fromdynamic logic to static logic, to enable 32.768 kHzreal-time clock frequency operation mode.
Theregister-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL)[57][58][59]on the Falcon Simulator software, which are NEC'sin-houseCAD tools.This methodology is the same as that used for theNEC V60.[60]In the late 1980s, theVerilog HDL had not yet been acquired byCadence Design Systems.[61]FDL had been used until the middle of the 2000s, and was also used for the development of NEC'ssuper-computer namedEarth Simulator.[62]
The difference from V60 is that thecircuit diagram was written with aschematic editor, not ofCalma but ofMentor Graphics, called NETED,[63]a part of the Design Architect product[64][65]onApollo Computer'sworkstation, which was the major schematic editor at that moment.[66]It enabled designers to generatenetlists, such asEDIF andSPICE, forLVS programs like Cadence'sDracula products, and NEC's in-house Zycad netlist forlogic simulation. Later on, this circuit diagram of NETED was able to generate agate-level Verilog HDL netlist for V850.
Most of the register-transfer-level FDL netlist was translated to the gate-levelschematic by hand, because thelogic synthesis had not yet to be practical.The FDL was precisely divided into datapath and random logic. For the datapath part,the gate-level circuit diagram enabled manually repeatedartwork. On the other hand, for the random logic part, logic synthesis was tried for generating gate-level schematic, but it was only about 10% of the total circuit.
In addition,formal verification was also not yet practical, which meant that fullregression test bydynamic logic simulation was required for the gate-level netlist to compare with the RTL one. For gate-level logic simulation, NEC's in-house CAD tool V-SIM was usually used.[67]But sometimes ahardware emulator, such as Zycad LE simulation accelerator,[68]was used for this purpose.(Refer to:.[69]: 13 In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.[70])
The basis of the V810 and V850 has a typicalgeneral-purpose registers-basedload/store architecture.[71]: 4 There are 32 32-bit general-purpose registers. Register 0 (R0) is fixed as the Zero Register which always contains zero.In the V850, R30 is implicitly used by thesld andsst instructions. 16-bit short-format load/store instructions useelement pointer (ep), where theaddressing mode comprises the base address register ep and immediate-operand offsets.In V850E or latermicroarchitectures, R3 is implicitly used byPREPARE/DISPOSE;call stack frame creation; and unwinding instructions, as astack pointer. Compilers'calling conventions also use R3 as the stack pointer.
The original V850 has a simple 5-stage 1-clock pitchpipeline architecture.[48]: 114–126 This is a significant feature ofreduced instruction set computers (RISCs). But the object-code size is about half that of theMIPSR3000,[71]: 5 because the V810 and V850 adopted 16-bit and 32-bit 2-way form-length instruction formats, respectively,[48]: 38–40 [71]: 17 [52]: 29–30 and most of the frequently used instructions are mapped onto a 16-bit half-word. In other words, a 16-bit external bus width is enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipment. This concept is similar toRenesas (formerly, Hitachi) SH,ARM Thumb, andMIPS16 instruction set architectures.[72]: 4
In addition, theinstruction set is carefully implemented. For example, to execute afunction call with a Jump and (Register) Link instruction,[48]: 61 [71]: 20 [52]: 64 which saves the nextprogram counter (PC) on a register (fixed to R31 in V810), is also one of the RISC techniques to reduce the number of instructions. Return from thefunction can be accomplished byjmp [Rn] (jmp [R31] in V810) instruction.[48]: 61 [71]: 23 [52]: 65 TypicalCISC processors use call and return instructions and push the next PC on theirstack memory area.
But V810 and V850 have some microarchitecture differences. The V810 adopts amicroprogram operation method for some instructions, such asfloating-point arithmetic andbit string operations, while the V850 uses a one-hundred-percenthardwired control method. As a result, for example, the first V850 does not have floating-point arithmetic andbit manipulation instruction sets, including the"find first one/zero" (search 1/0;SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.
Though the V800 series adopts a RISC instruction set architecture, theirassembly language ishand-coding friendly. They adopt a straightforward load/store architecture.[71]: 4 In addition, the "interlock" mechanism, both for thedata hazards and for thebranch hazards, are implemented:[71]: 33–35 in other words, an assembly language programmer does not need to consider anydelay slots. 32 general-purpose registers provide flexibility for assembly language users. A mixture of hand-assembled codes and C language compiled codes is facilitated by using compiler options, such as "-mno-app-regs" in theGnu Compiler Collection.[73]
TheIN instruction of the V810, which enables unsigned-load frommemory-mapped I/O, was removed from the first V850s.[71]: 22 [52]: 63
Detailed discussions are available in some old journals.[74][75]
The V850 series added many instruction set extensions, but all the extensions havebackward compatibility.[76]Therefore, older software designed for the previous versions of the V850 work on new V850 cores.
The first generation of the V850 does not haveunsigned load instructions, which had been removed from the V810 (where it was implemented withIN.H andIN.B). Then, in the second generation V850E (V850E1) Series, such unsigned functionality was again added (withLD.HU andLD.BU). In addition, the V850E has some other user-friendly "CISCy" extensions, such ascall table,switch, andprepare/dispose.[77]: 217
In 1996, the V853 was announced as the first 32-bit RISCmicrocontroller with integratedflash memory[78]but its maximum number of "erase and write" cycles was 16.[79]: 37
In 1998, NEC strategically started to expand the V850 product line, to standardapplication-specific standard product (ASSP),application-specific integrated circuit (ASIC), andsystem on a chip (SoC) businesses.[80]
In 2001, NEC launched the V850ES core, which is an ultra-low-power series, but is ISA-compatible with the V850E.[81]
Around 2001, the Java Acceleration IP core for the V850 seemed to be provided to some customers in SoCs[82]but detailed information is only found in some patents.[83][84]
In 2005, NEC Electronics introduced the V850E2 core as the V850E2/ME3 product line withsuper-scalar architecture.[85]
In 2009, NEC Electronics introduced the V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.[86]
In 2011, Renesas first introduced the SIMD extension for the V850 into the V850E2H core.[76][87]As for the SIMD extension, some academic studies were done on instruction encoding and efficient SIMD code generation.[88] It was later added into the V850G3H, V850G3KH and other H-extension cores before Renesas changed the V850 name to "RH850". Unfortunately, there is almost no publicly available documentation for these cores because Renesas gated them undernon-disclosure agreements (NDAs) that were only signed by automotive manufacturers.
The original V810 and V850 CPU architecture is designed for ultra-low power applications.
The V810 is described in detail in some journals.[89][90]
According to Renesas's documentation, thepower consumption of the V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.[5]: 14, 15
The V810 was one of the most low-power 32-bit microcontroller products of the early 1990s. It operates at from 2.2 V to 5.5 V with a 5 V 0.8 μm (CZ4) fabrication process.[91]Measured with Dhrystone MIPS, power dissipation is 500 mW at 15MIPS and 40 mW at 6 MIPS, at 5 V and 2.2 V, respectively. This specification can be achieved both by well considered instruction-set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of which are the benefit of a simplified RISC architecture.
This ultra-low-power architecture was succeeded by V850/Sxn product line, which are still being mass-produced after 20 years. Most of the improved chips are produced using a 3.3 V, 0.35μm (UC1) fabrication process, where the CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz (sub-oscillator) to 16.78 MHz (main-oscillator) with internal oscillator amplifier plus external resonator (crystal or ceramic).[10]Its power dissipation is 2.7 mW/MIPS at 3.3 V when made with a 0.35 μm (UC1)fabrication process, and 3.6 mW/MIPS at 5 V with a 0.35 μm (CZ6) fabrication process. "Software STOP" stand-by mode for the mask ROM version of V850/SA1, whose internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator (IDD6), consumes typically only 8 μA electrical current. Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum. (IDD5)[92]: 440, IDD5 [13]Its 1.8 V typical CPU operating current at 32.768 kHz might be 22 μA (40 μA ÷ 3.3 V × 1.8 V), where power dissipation should be 40 μW. It corresponds to 1.0 mW/MIPS (40 μW ÷ 0.032768 MHz ÷ 1.15 DMIPS/MHz ÷ 1000).
The V850/Sxn product line is also tuned for low noise, with bothEMI and withEMS. The V850/SB1 and SB2 are especially tuned for low EMI noise with a 5 V internal voltage regulator, which facilitates high sensitivity in receivingRF for car radios.[93]: 41–44
In 2011, NEC launched the 3rd generation microarchitecture V850ES ultra-low-power series, which achieves 1.43 mW/MIPS at an operating voltage range of from 2.2 V to 2.7 V,[81]but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture.Its "Sub-IDLE" stand-by mode for the mask ROM version of V850ES/SA2 and V850ES/SA3, whose internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator (IDD6), consume typically only 5 μA electrical current. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consumes typically 40 μA, 100 μA at the maximum.[94]: 509 Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA (40 μA ÷ 2.5 V × 2.2 V), where power dissipation should be 68 μW. This is about 1.7 times that of V850/SA1. It corresponds to 1.6 mW/MIPS (68 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000).
The V850ES/JG3-L product line has ultra-low-power variants, the μPD70F3792, 793, and the μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with typical electrical current of 18 μA at 32.768 kHz,[95]: 1002, 1041 which should be 22 μW at 2.0 V (18 μA × 2.0 V ÷ 3.3 V × 2.0 V). This corresponds to 0.52 mW/MIPS (22 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode power consumption, with watch timer, should be typically 3.4 μW at 1.8 V (3.5 μA ÷ 3.3 V × 1.8 V × 1.8 V).[95]: 1002, 1041
The power consumption of the NA85E2 (V850E2) core is much larger compared with the NU85E (V850E1) core using the same CB-12L (UX4L)[91][96]fabrication process. The reason is that the V850E2x core has a 128-bitinstruction prefetch bus and more than oneinstruction prefetch queue,[97]: 16 while the average instruction length of the V800 series is 16 bits.[71]: 17 It means 16 instructions can be fetched from the memory at once, and the memory and prefetch circuits sleep fors 3 to 7 cycles for dual-pipelinesuperscalar architecture. This gap enlarges electrical current amplitude differences.In addition, the peakelectric current exceeds allowances for thevoltage stabilizers of mobilegadgets.As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times that of former generations, although it should be able to take advantage of newfabrication process technologies.[86]Some mobile equipment avoids using dual-instruction execution (dual-pipelinesuperscalar), adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.
Eachopcode (operation code) table is fromUser's Manual: Architecture (refer toexternal links.).
In instruction.Arithmetic andlogical instructions are not fully, but relatively,orthogonal.SAT which checks flags (Overflow,Sign,Zero, andHalf-word) and rewrites the specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.| Bit[12:10] [15:13, 9] | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | Format |
|---|---|---|---|---|---|---|---|---|---|
| 000 X | MOV | ADD | SUB | CMP | SHL | SHR | JMP | SAR | I(R,r) |
| 001 X | MUL | DIV | MULU | DIVU | OR | AND | XOR | NOT | |
| 010 X | MOV | ADD | SETF | CMP | SHL | SHR | SAR | II(imm5,r) | |
| 011 X | TRAP | RETI | HALT | LDSR | STSR | Bit str. | |||
100 0 100 1 | Bcond | III(disp9) | |||||||
| BV | BZ/BE | BN(BS) | BLT | BNV | BNZ/BNE | BP(BNS) | BGE | ||
| BC/BL | BNH | BR | BLE | BNC/BNL | BH | NOP | BGT | ||
| 101 X | MOVEA | ADDI | JR | JAL | ORI | ANDI | XORI | MOVHI | IV/V |
| 110 X | LD.B | LD.H | LD.W | ST.B | ST.H | ST.W | VI(disp16[R],r) | ||
| 111 X | IN.B | IN.H | CAXI | IN.W | OUT.B | OUT.H | Float | OUT.W | VI/VII |
NOP is an alias ofNon-BR.| Bit[7:5] [10:8] | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | Format |
|---|---|---|---|---|---|---|---|---|---|
| 000 | MOV | NOT | DIVH | JMP | SATSUBR | SATSUB | SATADD | MULH | I(R,r) |
| 001 | OR | XOR | AND | TST | SUBR | SUB | ADD | CMP | |
| 010 | MOV | SATADD | ADD | CMP | SHR | SAR | SHL | MULH | II(imm5,r) |
| 011 | SLD.B | SST.B | IV(disp7[ep],r) | ||||||
| 100 | SLD.H | SST.H | IV(disp8[ep],r) | ||||||
| 101 | Bit[0] SLD.W / SST.W | Bit[3:0] Bcond | IV/III | ||||||
| 110 | ADDI | MOVEA | MOVHI | SATSUBI | ORI | XORI | ANDI | MULHI | VI(disp16[R],r) |
| 111 | LD.B | 2nd Map | ST.B | 2nd Map | JARL | Bit[15:14] SET1/NOT1 /CLR1/TST1 | 2nd Map Extension | V/VII/VIII | |
NOP is an alias ofMOV R0,R0.| Bit[23:21] | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | Format |
|---|---|---|---|---|---|---|---|---|---|
| [16] | 1st Map Bit[10:5]=111001 | ||||||||
| 0 | LD.H | VII | |||||||
| 1 | ST.H | VII | |||||||
| [16] | 1st Map Bit[10:5]=111011 | ||||||||
| 0 | LD.W | VII | |||||||
| 1 | ST.W | VII | |||||||
| [26:24] | 1st Map Bit[10:5]=111111 | ||||||||
| 000 | SETF | LDSR | STSR | undef | SHR | SAR | SHL | undef | IX(R,r) |
| 001 | TRAP | HALT | RETI | 1st Map Bit[15:13] EI/DI undef | Illegal instruction | X | |||
| 01X | Illegal instruction | — | |||||||
| 1XX | Illegal instruction | — | |||||||
| Bit[7:5] [10:8] | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | Format |
|---|---|---|---|---|---|---|---|---|---|
| 000 | —† | NOT | SWITCH | JMP | ZXB | SXB | ZXH | SXH | I(R,r0) |
| MOV | DBTRAP | Bit[4] SLD.BU /SLD.HU | SATSUBR | SATSUB | SATADD | MULH | I(R0,r31) / IV | ||
| undef | I(R0,r) / IV | ||||||||
| DIVH | I(R,r) / IV | ||||||||
| 001 | OR | XOR | AND | TST | SUBR | SUB | ADD | CMP | I(R,r) |
| 010 | CALLT | ADD | CMP | SHR | SAR | SHL | undef | II(imm5,r0) | |
| MOV | SATADD | MULH | II(imm5,r) | ||||||
| 011 | SLD.B | SST.B | IV(disp7[ep],r) | ||||||
| 100 | SLD.H | SST.H | IV(disp8[ep],r) | ||||||
| 101 | Bit[0] SLD.W / SST.W | Bit[3:0] Bcond | IV/III(disp9) | ||||||
| 110 | ADDI | Bit[15:11] MOV(r=0) | Bit[15:11] DISPOSE(r=0) | ORI | XORI | ANDI | Bit[15:11] undef | VI(imm16,R,r) /VI(imm32,R) /XIII | |
| MOVEA | MOVHI | STASUBI | MULHI | ||||||
| 111 | LD.B | 2nd Map | ST.B | 2nd Map | Bit[15:14] SET1/NOT1 /CLR1/TST1 | 2nd Map | VII(disp16[R],r) /VIII(imm3,disp16[R]) | ||
NOP is an alias ofMOV R0,R0.| Bit[23:21] [16, 26:24] | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111 | Format |
|---|---|---|---|---|---|---|---|---|---|
| 1st Map Bit[10:5]=111001 | |||||||||
| 0 XXX | LD.H | VII(disp16[R],r) | |||||||
| 1 XXX | ST.H | ||||||||
| 1st Map Bit[10:5]=111011 | |||||||||
| 0 XXX | LD.W | VII(disp16[R],r) | |||||||
| 1 XXX | ST.W | ||||||||
| 1st Map Bit[10:5]=11110X | |||||||||
| 0 XXX | 1st Map Bit[15:11] JR(r=0) / JARL (r≠0) | V(disp22) | |||||||
| 1 XXX | 1st Map Bit[15:11] PREPARE(r=0) / LD.BU | XIII/VII(disp16[R],r) | |||||||
| 1st Map Bit[10:5]=111111 | |||||||||
| 0 000 | SETF | LDSR | STSR | undef | SHR | SAR | SHL | Bit[18:17] SET1/NOT1 CLR1/TST1 | IX(R,r) IX(R,[r]) |
| 0 001 | TRAP | HALT | Bit[18:17] RETI/CTRET /DBRET /undef | 1st Map Bit[15:11] EI/DI undef | undef | X | |||
| 0 010 | SASF | Bit[17] MUL(R,r,w) /MULU(R,r,w) | Bit[17] MUL(imm9,r,w) /MULU(imm9,r,w) | Bit[17] DIVH(R,r,w) /DIVHU(R,r,W) | Bit[17] DIV(R,r,w) /DIVU(R,r,w) | IX(R,r) /XI(R,r,w) /XII(imm9,r,w) | |||
| 0 011 | CMOV(imm5,r,w) | CMOV(R,r,w) | Bit[18:17] BSW/BSH HSW/undef | undef | Illegal instruction | XI(c,R,r,w) /XII(c,imm5,r,w) | |||
| 0 10X | Illegal instruction | ||||||||
| 1 XXX | LD.HU | VII(disp16[R],r) | |||||||
| CPU core | Product variants | GCC targeting options[98] | Remarks |
|---|---|---|---|
| V810[1] (1991) | V810 family (V810, V805 V820, V821[99]) | Revert patch required.[53] Available on Planet Virtual Boy. GCC named gccVB. | Obsoleted products. Unsigned & signed load. μcoded float (single)[100] 1 KBI-cache. 5-stage pipeline.[101] 6.7 mW/MIPS (5 V Product) |
| V830[102] (1997) | V830 family (V830 — V833[54][102][103]) | ditto | Obsoleted products. High end products. Multimedia extension. 16 KB on-chip memory. Multiply accumulate. Saturation arithmetic Branch prediction.[104] |
| V850 (1994) | V850 family started V851 — V852[105] V853,[78][106][107] V854 | none or -mv850 | Obsoleted products. 5-stage pipeline. 4.4 mW/MIPS (5 V product) |
| V850 (1997) | V850/xxn (e.g. V850/SA1) | none or -mv850 | Not for new developments. Signed load. 1.15 Dhrystone MIPS/MHz Ultra-low power products. 3.6 mW/MIPS (5 V product) 2.7 mW/MIPS (3.3V product) 1.0 mW/MIPS (1.8 V Sub-ope.) |
| V850E (1996) | V850E/MS1,[108][109] V850E/MS2 | -mv850e | Not for new developments. Unsigned & signed load. 1.3 Dhrystone MIPS/MHz Standard products. |
| V850E1 (1999) | V850E/xxn (e.g. V850E/MA1[22]) NB85E SoC core[110][111] NU85E SoC core[110][111] (Sony's & NEC's best-cellular.) | -mv850e1 or ‑mv850es | Unsigned & signed load. N-Wire and N-Trace. Standard products. SoC Products. |
| V850ES (2002) | V850ES/xxn(-x) (e.g. V850ES/SA2) | -mv850es or ‑mv850e1 | Unsigned & signed load. Ultra-low power products. 1.43 mW/MIPS (2.5 V product) 0.52 mW/MIPS (2.0 V Sub-ope.) Shift to V850E2S requested. |
| V850E1F (2005) | V850E/PH2, V850E/PH3 V850E/PHO3 | Patch required (maybe). | H/W float (single precision). |
| V850E2 (2004) | V850E2/ME3 NA85E2 SoC core[110][112] (NEC's long-running cellular. Sets life = 2004–2012.) | -mv850e2 | Not for new developments. Many errata but still alive. Single insn. executing. (Dual-executing errata.) 7-stage pipeline. S/W float. Standard Products. SoC Products. |
| V850E2(v2) () | V850E2/xxn (e.g. FIX ME) NB85E2 SoC core[110][112][113] | -mv850e2 | Errata cleaned up. Dual instruction executing. 7-stage pipeline. S/W float. Standard Products. SoC Products. |
| V850E2M (2009) G3 | V850E2/xxn (e.g. V850E2/FG4) RH850/nxn | -mv850e2v3 and -msoft-float | S/W float. Dual instruction executing. 7-stage pipeline. 2.56 Dhrystone MIPS/MHz 1.5 mW/MIPS Multi CPU core support. Memory Protection. |
| V850E2R (2010) G3R | V850E2/xxn (e.g. V850E2/MN4) RH850/nxn | -mv850e2v3 | H/W float (double precision). Dual instruction executing. 7-stage pipeline. 2.56 Dhrystone MIPS/MHz Multi CPU core support. Memory Protection. |
| V850E2S (2011) G3K | V850E2/xxn(-x) (e.g. V850E2/Jx4-L) (e.g. V850E2/Fx4-L) RH850xnx | -mv850e2v3 and ‑msoft‑float | S/W float. 5-stage pipeline. 1.9 Dhrystone MIPS/MHz Multi CPU core support. Memory Protection. Ultra-ultra-low power. Standard products. V850ES/xxn pin compat. Automotive products. Shift to RH850 requested. |
| V850E2H (2010)[114] V850E3 (2014) G3M G3MH, G3KH | RH850/xnx (e.g. RH850/C1H) | -mv850e2v4 and ‑mloop or -mv850e3v5 and ‑mloop | SIMD extension. 64-bit multiple load/store. Loop extension. H/W float (double precision). Memory Protection. Multi CPU core support. Automotive products. |
[99][103][108][109][1][101][53][105][106][107][110][114]
In 1998, NEC started to provide the V850 family as anASIC core, to expand its ASIC business.[115]In addition, both the V850E1 CPU core named Nx85E[116][117]and the V850E2 CPU core named Nx85E2,[118]are also used for expanding its ASIC products business.
VariousSoCs utilize this core. In 2003, for example, Dotcast, Inc. used the NU85E core for aset top box receiver ofdigital datacasting based on thedNTSC (data inNTSC video method[119]). This core is fabricated with CB-10 0.25μm 5-layered-metal process technology.[120]: 9–10
The NA85E2C core, which is developed using a 1.5 V 150 nm CB-12L (UX4L) fabrication process,[91][96]has manyerrata (4 pages appendix in preliminary architecture manual,[121]: 230–233 plus a further, 7-page restrictions document[122]),but which doesn't seem to matter, because this is a product with a long lifespan.
NEC also expanded production of a core using a 130 nm CB-130 (UX5) fabrication process,[91]cell-base IC.[123][124]
Synopsys DesignWare IP core for V850E was once announced,[125] but support has been discontinued.[126]
| Name | Core | Cell-base series | Power supply | Node/ Gate L | Fab. proc. [91] | Freq. MHz | Type | ICE | Docs. |
|---|---|---|---|---|---|---|---|---|---|
| NA851C | V851 | CB-9VX | 3.3 V | 350 nm | UC1 | 33 | With peripheral | [115][127] | |
| NA853C | V853 | CB-9VX | 3.3 V | 350 nm | UC1 | 33 | With peripheral | [115][128] | |
| NA85E | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | Bulk core | [116] | ||
| NB85E | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | 66 | Bulk core | [129][130] | [115][117][131] |
| NB85ET | V850E1 | CB-9VX | 3.3 V | 350 nm | UC1 | 66 | w/ Trace I/F | [129][130] | [115][131] |
| NB85E | V850E1 | CB-10 | 2.5 V | 250 nm | UC2 | 66 | Bulk core | [129][130] | [131] |
| NB85ET | V850E1 | CB-10 | 2.5 V | 250 nm | UC2 | 66 | w/ Trace I/F | [129][130] | [131] |
| NU85EA | V850E1 | CB-10VX | 2.5 V | 250 nm | UC2 | 100 | Bulk core | [129][130] | [131][132][133][134] |
| NU85ET | V850E1 | CB-10VX | 2.5 V | 250 nm | UC2 | 100 | w/ Trace I/F | [129][130] | [131][132][133][134] |
| NDU85ETV14 | V850E1 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | w/ Trace I/F | [129][130] | [131][132][133] | |
| NDU85ETVxx | V850E1 | CB-12M | 1.5 V | 150 nm/ 130 nm | UX4M | w/ Trace I/F | [129][130] | [131][132][134] | |
| NA85E2C | V850E2 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | 200 | w/ Trace I/F | [112][135] | [131][134] |
| NB85E2C | V850E2 | CB-12L | 1.5 V | 150 nm/ 130 nm | UX4L | 200 | w/ Trace I/F | [112][135] | [131][134] |
| V850E2x | CB-130L | 1.2 V | 130 nm/ 95 nm | UX5L | |||||
| — | — | CB-90L | 1.2 V | 90 nm/ | UX6L | Replaced by ARM946.[113] | |||
| In-house | V850E2x | UX6LF | 1.2 V | 90 nm/ | UX6LF | Renesas internal use only ??? | |||
| — | — | CB-65L | 1.2 V | 65 nm/ | UX7L | Skipped. Replaced by ARM1156.[113] | |||
| — | — | CB-55L | 1.2 V | 55 nm/ 50 nm | UX7LS | Skipped. Replaced by ARM Cortex-M3. | |||
| — | — | CB-40L | 1.1 V | 40 nm/ 40 nm | UX8L | Replaced by ARM Cortex-M4. | |||
| In-house | V850E3 | RV40F | 1.1 V | 40 nm/ 40 nm | RV40F | 320 | Renesas internal use only ??? |
FPGA prototyping systems for V850E1, V850E2, and V850E2M core-based SoCs were intensively developed to expand the SoC business. They comprised a V850 CPU core LSI (TEG, or Test Element Group) board and FPGA add-ons. Most SoC products were for mobile equipments, because thepower dissipation of original V800-Series RISC architecture was much lower compared withCISC.[1][5][101] It is similar to theARM architecture that is widely used for mobile gadgets.
Around 2011–2014, Renesas Electronics extensively expanded the V850E2 product line,[146][147]but this high-paced expansion brought much confusion. For example, as of 2018, some have requested that V850E2/xxn products be replaced with RH850/xnx ones.[148]
In addition, in 2012 Renesas started to intensively promote the migration from ten-year-old V850ES/Jx3 product lines to the newly produced V850E2/Jx4, such as for Ethernet and USB applications,[149][150]but the newer products are not listed on their website, as of 2018.[39]
Currently,[as of?] Renesas Electronics is designing a "dual" "lockstep" system, but its predecessor NEC V60-V80 had "multiple modular" lockstep mechanism called FRM,[151]either with roll-back by "retry" or with roll-forward by "exception" for each fault detected instruction.
In addition, the NEC V60-V80 has several implementations ofUNIX System V port product releases, one of which is "real-time UNIX RX/UX-832"[152](here, 832 stands for the μPD70832 (V80), not V832). Its multiprocessor implementation is called MUSTARD (Multiprocessor Unix for Embedded Real-Time Systems), which can operate a maximum of 8 processors simultaneously, and its lockstep mechanism was dynamically configurable.[153]
In 2001, bothNEC Corporation andSynopsys, Inc., announced they had agreed to promote the V850E as DesignWare IP core.[125][126]But as of 2018, the V850E is not listed on DesignWare libraries.[154]
Lucent Technologies andTexas Instruments once licensed the V850 and V850E SoC cores, respectively,[155][156][157][158]but those devices cannot be found.
In 2006,Metrowerks developed theCodeWarrior compiler for the V850, which was one of the main compilers for the V850,[159]but around 2010, they discontinued support.
Also in 2006, NEC did not give any roadmap for the V850 family as SoC cores.[113] The V850E2 core, developed in 2004, was described as the last, best core for SoC applications. However, NEC introduced ARM9 (arm v5) and ARM11 (arm v6), especially for mobile equipment.This decision suddenly decreased the net profit of LSI devices, because of the royalty for using ARM, and thus price competition with other ARM SoC providers. The sales revenue of "V850 total solutions", such as development tools, real-time OS, middle-ware packages, and in-circuit emulators, also decreased. The number of V850 devices sold also suddenly decreased, because mobile equipment manufacturer were the major customers of V850E1 and V850E2 cores at that moment.[160]
In 2008, KMC (Kyoto Mictocomputer), which is one of the major and of the first providers of in-circuit emulators for the V850 family, announced "exeGCC" being updated from Rel. 3 to Rel. 4,[161]but it excluded the V850 from this updating list, which added PowerPC and ARM v7. KMC chose SH-4A and ARM v7, instead of V850 and RH850,[162]though it had been working closely with NEC and Renesas Electronics.[159]
The V850 CPU cores runuClinux,[163]but on October 9, 2008,Linux kernel support for the V850 was removed in revision 2.6.27.,[164] because NEC stopped its maintenance.[165][166][167]The person in charge of V850 Linux kernel maintenance was moved from NEC to Renesas by its merger, but his new job was compiler design and never returned to Linux kernel maintenance.[168]This corporate decision prevented the possibility of porting toAndroid.[169]As of 2018, Renesas Electronics mainly focuses Linux kernel support on SH3/SH4 and M32R processors.[170][171][172][173][174]
V850Operating systems are mostlyreal-time.
Some operating systems require amemory protection unit (MPU) to dividetasks (orthreads) strictly forreliability and safety reasons. In such cases, the v850e2v3 (Gen. 3)microarchitecture, or above, is required.
ITRON is anopen standard specification ofreal-time OS (RTOS), which is major in Japan.Its specification is defined under the leadership ofKen Sakamura, as a part ofTRON project, the initialr I standing for "Industrial". Because the ITRON specification defines interface and skeleton only, each vendor has its own implementation.
AUTOSAR is anopen systems architecture ofoperating system for theautomotive industry. Its purpose is to standardizeelectronic control units (ECU) forautomotive engines.AUTOSAR is an upward compatible specification ofOSEK/VDX, which is also a Germanconsortium established in 1993.
In Japan, this research was started in 2006, as a joint project byJAIST andDENSO. Renesas Electronics joined this project in 2009.[191]Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is a strategical product of Renesas Electronics. However, its documentation is only available in Japanese, as its main customer isToyota Motor Corporation.
Variousmiddlewareapplication softwares are provided from various vendors.
Most of the compilers, for both for the V850 family and the RH850 family, are exactly the same product, and extendedISA targets are controlled by command line options.[213][214]
Compilers for the V850 family and the RH850 family include:
Usually, dis-assemblers are provided as a part of C compiler or assembler packages.
GUI basedprogramdebuggers are mainly provided fordebugging ofcompiledsource codes. Usually, it is used withinstruction set simulators orin-circuit emulators.
Instruction set simulator, in other words,Virtual Platform is provided to performdebugging without equipment'shardware before testing on a real machine.
Automated code reviewer, in other words,sourcecode analyzer qualify the level of completeness of written softwaresource code. This method is classified asdynamic code analysis andstatic code analysis.
IDE,Integrated Development Environment, is a framework to provide software development functions.
Mostin-circuit emulators, such as Renesas'sIE850 (formerlyIECUBE2),[251]can be used for both the V850 family and the RH850 family, but may requirefirmware updating.The latest "trace function" of theJTAG (N-Wire[252]) based in-circuit emulator is upgraded from theN-Trace (single-ended signaling)[253]to theAurora Trace (differential signaling).[254]
Full probing pod typein-circuit emulator is sometimes calledfull ICE orlegacy ICE.
N-Wire and N-Trace[258][253][259][260]is aJTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller),[261]primarily compiled byPhilips N.V. (currentlyNXP Semiconductors). But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor andin-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized byIEEE 1149.1 Working Group.[262]
Nexus orIEEE-ISTO 5001-2003 is a standarddebugging interface forembedded systems.
Aurora is a high speed signal transfer specification. Itsdata link layercommunications protocol is a point-to-pointserial links, andphysical layer is a high speeddifferential signaling.
Because the V850 family is developed as asingle chip microcontroller, every product integratesnon-volatile memory. In its first stage, it wasone-time programmable orUV EPROM type, but in V853, V850/xxn Series, and later, it becomesflash memory type.
Agang writer, or agang programmer, is an oldterminology forprogrammable ROMwriters, or programmers. Its name comes from that it steals the binary code from one device, and write it to several others simultaneously. Thisread device is sometimes called amaster device. For mass production use, a dedicated attachment board with "a set of sockets", i.e. "a gang", is needed. As usual, instead of a programmed master device, anobject code file can be copied from a PC via download cable, or from a USB stick. Mostgang writers acceptASCII-format files such asIntel HEX andMotorolaSREC, or binary format files such asELF.
This method is suitable for mass production.
Flash ROM programmingservice providers exist in most countries.
MostJTAG-basedin-circuit emulators have anon board flash ROM programming function via a debug port,
which may be according toIEEE standard 1532-2002, a standard for in-system configuration of programmable components.[280]
If the target board has aRS-232C connector and a transceiver (driver/receiver) IC, such asICL32xx,[281]for theUARTx peripheral function of V850 device, flash ROM programming with a directly connectedPC might be available (depends on devices[282]: 16–24 ).TheRenesas Flash Programmer softwareV2[283]orV3[284]is required.
On-board programming is also available viaUARTx orCSIx+HS peripherals on V850 devices by using dedicated programmer hardware (depends on devices[282]: 16–24 ).
To program V851[286]: 11, 14–20 and V852,[287]: 11, 14–20 an ancientPROM programmer with dedicated adapter is required.
Some gray zone hacking tools exist for V850 on car dashboards.
Abstract:
An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions. V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V.
The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
Built-in CPU functionality
• Onboard 32-bit RISC CPU (V850ES core)
• Built-in RAM (14KB)
• Power management functionality
• Built-in peripheral circuits (timer,interrupt controller, serial interface)
Summary:
We developed this product which carries new functions, CD( includes MP3CD playback), MagicGate Memory Stick (recording & playback & updating) and HDD (recording & playback), for the first time as a car audio product. This product for the worldwide market is packed into 1DIN size, with standard features (AM/FM Tuner, MOS-FET50Wx4ch amplifier, OrganicEL display, and sound field control DSP) and the new functions. We considered the operation carefully to handle many music files in the HDD easily. We concentrated on making a new field of audio entertainment, and we were the first to introduce this system on the car audio market.
Result: application refused
Result: application refused
Abstract:
An advanced 32-bit RISC microprocessor for embedded controls; V810 and its design technique are described in this paper. The V810 is fabricated by using 0.8μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7mm2 die. In design of the V810, we used design automation techniques. The V810 was analyzed for logical correctness and timing constraint before fabrication. Finally, V810 executed realtime-OS and SPEC benchmarks correctly at first silicons.
Abstract:
Progress of logic/layout synthesis makes it possible to design circuits by Hardware Description Languages (HDLs). When a designed circuit is small, it is synthesized automatically from HDL description. In this paper, to make it clear what kinds of problems are there in designing a large circuit looks like a processor, we design a processor and some components of it by HDLs in RT level and evaluate circuits synthesized by a logic/layout synthesis tool.
Design Architect by Mentor Graphics Corporation with programs NETED and SYMED. This system is the most universal one of the three [3.3].
Version C1 on HP Unix V10.20 is used (short form MENTOR)
Code size is an important factor in most embedded designs, and instruction sets are designed and extended with code size in mind. Fairly typically, the NEC V850 architecture uses 16-, 32-, 48-bit, and 64-bit instructions to encode a RISC-style instruction set. The 32-bit ARM and MIPS architecture have been extended with reduced 16-bit instruction sets in order to reduce the code size. Instructions that perform a lot of work, like loading multiple values from the stack, are popular to reduce code size.
All V850 products are upwards compatible. As a result, today's sophisticated components can still execute the same instructions as their forebears. The architecture has undergone continual improvements with extensions to the instruction set, and today it offers computing power of up to 2.6 Dhrystone MIPS/MHz. Further performance increases can be achieved by integrating several of these processor cores on a single chip, delivering twice or even four times more computing power.
The present invention relates to a method for use of a stack in a Java accelerator device.
With such arrangement, the microprocessor can flexibly deal with various kinds of instruction sets with different architectures such as an instruction set for an interpreter language for realizing a virtual machine for Java and an instruction set for emulating another microprocessor.
Abstract:
An advanced 32-bit RISC microprocessor for embedded control; V810 is introduced in this paper. The V810 has high performance and application specified functions.
V810 dissipates less power than any other RISC chips. The V810 is the first 32-bit RISC microprocessor that operates at 2.2 V.
The V810 chip is fabricated by using 0.8 μm CMOS double metal layer process technology to integrate 240,000 transistors on a 7.7×7.7 mm2 die.
From the V810 Seminar.
Summary:
A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 μm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 × 7.1 mm die.
NEC also will provide internally-developed V850E and VRx CPUs, though Mabuchi said he believes NEC will need to license the ARM9 core to address the market for mobile terminals.
A19354JJ1V1UM00
V850E2M CPU core，max. 266 MHz operation
Abstract:
This paper describes requirements for real-time UNIX operating systems, design concept and the implementation of RX-UX 832 real-time UNIX operating system for v60/v70 microprocessor which are NEC's 32-bit microprocessors. RX-UX 832 is implemented adopting the building block structure, composed of three modules, real-time kernel, file-server and Unix supervisor. To guarantee a real-time responsibility, several enhancements were introduced such as, fixed priority task scheduling scheme, contiguous block file system and fault tolerant functions.
Thus, RX-UX 832 allows system designers to use standard Unix as its man-machine interface to build fault tolerant systems with sophisticated operability and provides high-quality software applications on the high performance microchips.
Trying to compile the v850 port brings many compile errors, one of them exists since at least kernel 2.6.19.
There also seems to be no one willing to bring this port back into a usable state.
This patch therefore removes the v850 port.
If anyone ever decides to revive the v850 port the code will still be available from older kernels, and it wouldn't be impossible for the port to reenter the kernel if it would become actively maintained again.
Link missing for <www.ic.nec.co.jp/micro/uclinux/>
"We have developed a virtualization technology for our V850 architecture to control multiple systems on a single CPU core with no mutual interference, allowing high speed and composite control for industrial machinery and automotive, where real-time is essential. SYSGO enables us to achieve a scalable CPU architecture with virtualization technology that supports our customers in building flexible development systems." Michiya Nakamura, General Manager, 1st MCU Business Division, Renesas Electronic Corporation
NEWS HIGHLIGHTS
•Development process for Wind River Diab Compiler achieves Automotive SPICE Process Capability Level 2 certification.
•New Wind River Diab Compiler ISO 26262 Qualification Kit guides customers in qualifying Diab Compiler for safety-related projects.
•Diab Compiler adds support for Renesas RH850 family microcontrollers.
PARTNER Overview
PARTNER is a Window based source level debugger, which is developed as PARTNERWin by Kyoto Micro Computer Co., Ltd., and ported for the products of Midas lab Inc.
In addition to the basic functions as a source level debugger tool, such as program load, program execution, break point control, data display/change, code display/change, there are other functions customized for Midas lab products.
The vast majority of the competition's offerings have included a JTAG Test Access Port (TAP). Recently, products have been arriving with more enhanced capabilities, such as N-Wire/N-Trace from NEC, RISCWatch from IBM, and COP from Motorola. These versions of Enhanced JTAG perform relatively the same functions and use the traditional JTAG TAP with a couple additional pins for greater control.
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