Universal Chiplet Interconnect Express (UCIe) is anopen specification for adie-to-dieinterconnect andserial bus betweenchiplets. It is co-developed byAMD,Arm,ASE Group,Google Cloud,Intel,Meta,Microsoft,Qualcomm,Samsung, andTSMC.[1]
In August 2022,Alibaba Group andNvidia joined as board members.[2]
A common chiplet interconnect specification enables construction of largeSystem-on-Chip (SoC) packages that exceed maximumreticle size. It allows intermixing components from different silicon vendors within the same package and improves manufacturing yields by using smaller dies. Each chiplet can use a differentsilicon manufacturing process, suitable for a specific device type, or computing performance and power draw requirements.[3][4]
The UCIe 1.0 specification was released on March 2, 2022.[5] It definesphysical layer, protocol stack and software model, as well as procedures for compliance testing. The physical layer supports up to 32GT/s with 16 to 64 lanes and uses a 256 byteFlow Control Unit (FLIT) for data, similar toPCIe 6.0; the protocol layer is based onCompute Express Link with CXL.io (PCIe), CXL.mem and CXL.cache protocols.
Variouson-die interconnect technologies are defined, like organic substrate for a 'standard' 2D package, or embedded silicon bridge (EMIB),silicon interposer, and fanout embedded bridge for 'advanced'2.5D/3D packages.[3] Physical specifications are based on Intel's Advanced Interface Bus (AIB).[4][6][7]
Shorter signal paths allow the links to have 20× better I/O performance and power consumption (~0.5 pJ per bit) comparing to typical PCIeSerDes, with bandwidth density up to 1.35 TB/s per mm2 for a common bump pitch of 45 μm, and 3.24× higher density with a bump pitch of 25 μm.[3]
Future versions may include additional protocols, wider data links, and higher density connections.[3]
The UCIe 1.1 specification was released on August 8, 2023.[8]
Highlights:
The UCIe 2.0 specification was released on August 6, 2024.[9]
Highlights: