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Do we really need to cite each expected release? Since we cited that "Every year, there is expected to be one tick or tock.", we should be able to just do basic arithmetic.—Precedingunsigned comment added by68.57.72.229 (talk •contribs) 02:28, 17 February 2009

It helps explain the concept to the reader.--Intelati (talk)20:13, 23 July 2010 (UTC)[reply]

It's definitely present since Pentium II/III times - even theIntel chart hints at this on the left edge - possibly even longer:

--Zac67 (talk)14:14, 23 June 2011 (UTC)[reply]

My edit was undone[1].

I have added columns for Intel Atom and Intel Itanium - with links describing the relation between those chips and the Tick-Tock model. Yes, Atom and Itanium are not on the main Tick-Tock schedule, the roadmap from 2012 shows the Atom updated more frequently and Itanium less frequently than the main Tick-Tock schedule. Nevertheless we those are products fabricated at Intel facilities and as shown in the sources those are often presented together with the main Tick-Tock roadmap. In some sources the same terms (tick/tock) are used also for Atom and Itanium.

I have also added columns for Globalfoundries (factory for AMD products) and TSMC - to put Intel in perspective with those major semiconductor manufacturing competitors (and also their x86 fabless competitor AMD). I have also added a source about AMD going the "tick tock" way.

I propose restoring those columns.Ianteraf (talk)16:04, 7 February 2012 (UTC)[reply]

As far as I know, Intel's Atom, Intel's Itanium, AMD's x86 processors, GlobalFoundries, TSMC, are not processors designed with Intel's Tick-Tock strategy, therefore cannot fit in theRoadmap table (look at the first column). GlobalFoundries and TSMC are not even processors, but foundry semiconductor companies (the mix between processor release date and fabrication process release date is awfull). Several processors you placed are misplaced.

The only processors which can fit in Tick/Tock cells would be Cedarview, Medfield, Brisbane, Phenom II (all four being mostly die shrink of predecessors, without major improvement), altough "Brisbane" and "Phenom II" do not cover the whole cell of their AMD x86 processors column (should be "65 nm K8" and "45 nm K10" instead).

The 'source about AMD going the "tick tock" way' that you added does not describe something like Intel's Tick-Tock strategy with a 2 years period (one year: die shrink, next year: major improvements, and so on), but a 1 year period strategy. AMD has and will release new lineup in 2011, 2012 and 2013, with APU processor (Llano, Trinity,Kaveri) first (tick) and non-APU processor (Zambezi, Vishera) several month later (tock).

If you want to publish broader or different comparison tables, then please do it in separate tables, preferably in different pages. A table of fabrication process release among (surviving) foundry semiconductor companies would be (very) usefull somewhere in Category:Semiconductors.Visite fortuitement prolongée (talk)22:31, 7 February 2012 (UTC)[reply]

Of course dates/periods are different (that's why they were separately specified in the boxes), of course GF/TSMC are not processors (that's why there was a top-to-bottom vertial line separating those), of course Atom/Itanium don't followthe same schedule as "main" Intel chips (that's why there was a top-to-bottom vertial line separating those).

But the sources clearly show that Atom, Itanium and "main" Intels are all aligned together with the so called "Tick Tock model". This is especially obvious in the slide with Xeon tick-tocks and Itaniumtocks. It's just that Atom will be updated more frequently and Itanium less frequently than the "main" Intels.

The place for showing the cadence, relation and alignment between the three Intel architectures (as described in the roadmap sources) is right here, where most of it is already presented anyway. This requires simply the addition of Atom/Itanium columns. It's much worse to duplicate the same table in another article only to add these columns.

About "Brisbane" and "Phenom II"/K8/K10/etc. - I just put the first chip on a given process, we can tune those if you find some discrepancy. And yes, AMD cadence will not be the same as Intel's, but that's the point - to show how the two competing schedules align with each other. Also TSMC - adding one column here instead of duplicating the whole table elsewhere.

I wasn't aiming to make this a comparison for all semiconductor manufacturers - just put GF (as the other factory for x86) and TSMC (as one of the biggest process technology/factory competitors of Intel). I don't object adding others if you have information about those.Ianteraf (talk)09:14, 8 February 2012 (UTC)[reply]

"the sources clearly show that Atom, Itanium and "main" Intels are all aligned together with the so called "Tick Tock model"." (Ianteraf) I don't think so. The sources show that Atom and Itanium are using the 65/45/32 nm nodes (because Intel use those fabrication process for all its products, not 70 nm for some and 62 nm for some other) like mainline x86, nothing more. I suggests you to ask a second opinion.Visite fortuitement prolongée (talk)21:52, 8 February 2012 (UTC)[reply]

Yes, that's what I mean by "aligned".

Then all and every processors since 30+ years have been "aligned" with 2007 Intel's Tick Tock model, including all Intel/Cyrix/AMD x86, all Itanium, all 68000, all ARM. It looks like you are confusingIntel Tick-Tock's table andTemplate:Semiconductor manufacturing processes's table.Visite fortuitement prolongée (talk)21:16, 9 February 2012 (UTC)[reply]

Why do you disagree to add the relevant context to the "main" Intels and insist on showing "Mains Tick-Tock" in vacuum? You see, the sources are doing exactly that - showing the context (between Intel-AMD, "mains"-Atom and eventocks for Itanium, etc.)Ianteraf (talk)07:37, 9 February 2012 (UTC)[reply]

I do not disagree to contextualize Intel's Tick-Tock strategy. I do disagree to add, in a table which first column is "Architectural change", "Tick", "Tock", "Tick" (...), cells which do not fit with that. As showed in the"recent x86 processors" table here, only Intel's x86 mainline since 2006/65 nm do Tick/Tock/Tick and fit.Visite fortuitement prolongée (talk)21:16, 9 February 2012 (UTC)[reply]

Yes, that's why I separated those with a top-to-bottom vertical line, to separate the contextual from the main Tick-Tock columns.Ianteraf (talk)18:18, 10 February 2012 (UTC)[reply]

Also, there's a similar problem with the current "release date" column - it gives thefirst release date, but each column has a different release date.Ianteraf (talk)18:31, 10 February 2012 (UTC)[reply]

Confusing and unrelated to the article topic. What's the point?BroderickAU (talk)08:08, 9 February 2012 (UTC)[reply]

"What's the point?" (BroderickAU) Showing Ianteraf which table wouldn't be bogus in my opinion. I'll hide this.Visite fortuitement prolongée (talk)21:16, 9 February 2012 (UTC)[reply]

Not bad tables, but I don't see how we can fit those here... Any ideas?Ianteraf (talk)18:18, 10 February 2012 (UTC)[reply]

Intel has announced that they are applying their tick-tock strategy to Atom starting with Silvermont. Please see the reference I added to the article. In other Intel announcements their new CEO "BK" has stated some Silvermont and Airmont cores will likely get marketed within their Celeron and Pentium segments; specific details have not been released.50.53.15.59 (talk)04:47, 22 July 2013 (UTC)[reply]

The forecasts about 2015 Atom are forecasts. And actually only one forecast has been told until now. And even if the 2015 Atom were following "Tick-Tock" model, the previous are not.Visite fortuitement prolongée (talk)20:45, 22 July 2013 (UTC)[reply]

P6 and Netburst obviously did not follow the tick-tock model. A similar statement about forecasts could be said about much of the current tick-tock roadmap for later entries as they too are but forecasts (and subject to possible change). That said, Intel's public statement about applying their tick-tock cadence to Atom starting with Silvermont is well documented by a great number of media releases so it is hardly unsubstantiated. As such I believe it meets the criteria for notable and inclusion within Wikipedia despite your insistence to delete such content. Face it; Atom and Tick-Tock now do go together whether you like that situation or not.50.53.15.59 (talk)14:51, 23 July 2013 (UTC)[reply]

"P6 and Netburst obviously did not follow the tick-tock model." – the term wasn't invented yet but the strategy was largely the same, seeabove.Zac67 (talk)17:59, 23 July 2013 (UTC)[reply]

I agree the term was not invented yet but I am not sure I agree that they were much the same. Especially for Netburst which crosses four fab technologies so seems to stray far from any tick-tock cadence. For P6 things are a little better if you consider Pentium M and Enhanced Pentium M as new uarchs and not as P6 shrinks (which is debatable) but it still does not really adhere to a tick-tock cadence.50.53.15.59 (talk)23:37, 23 July 2013 (UTC)[reply]

The new marketing names have a generation number as well as the i3/i5/i7 (which is just market segment). Should that be shown somehow?— Precedingunsigned comment added by86.134.216.240 (talk)17:17, 3 February 2013 (UTC)[reply]

I second this. The Intel datasheets for these processors don't use any of the terms on this table.JonathonReinhart (talk)04:51, 10 January 2014 (UTC)[reply]

I've been trying to add this information, but I have had to contend with edit warring. Ultimately some of the information survived, but not without: damage to table formatting, destruction of two references, destruction of the information about what the 1st generation would have been (in retrospect), duplication of "Core" and inverted order when placed next to a column containing "Core [...]", unnecessary replication of the Marketing Names (making the table unnecessarily taller), and wrongful exclusion of Core M (and apparently also Celeron and Pentium, with only Xeon left out of the scheme). This is ridiculous: somebody apparently claims total ownership of this article, and keeps destroying other people's edits and generally creating a mess. --RFST (talk)04:13, 2 May 2015 (UTC)[reply]

These^[1][2] are the references that were (repeatedly) thrown away, with the first reference explaining why Intel deprecates use of code names around launch time (also providing good cause for why the product names shouldn't be relegated to the far right of the table!), and the second reference showing where the numbering started (1st generation being Nehalem and Westmere together). So what do I do now? I have no patience to fight a (recidivist!) edit warrior... --RFST (talk)14:58, 2 May 2015 (UTC)[reply]

• Thefirst source that you give is a 2012 Intel press release, forecasting that when Intel will launch its 22nm Haswell processors, all will be labelled as "4th Generation Intel Core", not only the "Core ix" processors. When Intel actualy launched its 22nm Haswell processors, in 2013, only the "Core ix" processors where labelled "4th Generation Intel Core".
• Thesecond source that you give is aquora.com article by some "x-ray applications engineer", and is not a reliable source.
• A search in Google image give plenty of Intel slides showing "yth Generation Intel Core ix", whitout mention of Core M, Pentium, Celeron, Xeon ([[2],[3],[4],[5],[6],[7],[8],[9],[10],[11],[12],[13],[14],[15],[16])
• http://ark.intel.com/ main page show links to "4th Generation Intel® Core™ i7 Processors", "3rd Generation Intel® Core™ i5 Processors", "Intel® Pentium® Processor", "Intel® Core™ M Processors", etc, and no "yth Generation Intel® Pentium® Processors" at all.
• The "yth Generation Intel Core" labell only "Intel Core ix" processors. It does not labell Core M, Pentium, Celeron, or Xeon processors, period.
• The 4 table:Special:PermanentLink/656812054#Roadmap,Special:PermanentLink/657174584#Roadmap,Special:PermanentLink/656813082#Roadmap,Special:PermanentLink/660296940#Roadmap.

Visite fortuitement prolongée (talk)20:42, 2 May 2015 (UTC)[reply]

Apparently Core M etc. are not included in the scheme after all, but I only mentioned that here on this Talk page, after you deleted a column with the header explicitly saying "(Core only)", only to substitute an unsightly mess! I stand by my other complaints, including about destroying the references (your supposed justifications have no merit). --RFST (talk)03:54, 4 May 2015 (UTC)[reply]

"Conroe/Merom" is not a microarchitectural codename but rather codenames for core instances of the Core microarchitecture. I am open to discuss this but I see no rationale for such a nomenclature.50.53.15.59 (talk)04:16, 22 July 2013 (UTC)[reply]

What are you talking about? "Conroe/Merom" isa codenames??Visite fortuitement prolongée (talk)20:45, 22 July 2013 (UTC)[reply]

I am saying "Conroe" and "Merom" are codenames for specific microprocessor chips (that get binned, packaged and marketed as a number of microprocessor products) and not microarchitectural CPU core codenames. "Core" is the microarchitecture CPU codename of the core used within both Conroe and Merom chips (unfortunately this is further confused by Intel marketing a number of other things under the separate "Core" brand name; e.g., Enhanced Pentium M based Yonah microprocessor chips). So Conroe and Merom are valid chip codenames based on the microarchitectural core codenamed "Core". Terms like "core" are confusingly used in different ways within media. That is what I am saying.50.53.15.59 (talk)14:45, 23 July 2013 (UTC)[reply]

Ok, nice. I agree with that.Visite fortuitement prolongée (talk)20:14, 23 July 2013 (UTC)[reply]

If you agree with that then why edit the box back to "Merom"? Yes, I can see the one reference have added that shows "Merom" as a microarchitecture within a tick-tock slide but sinceIntel Core (microarchitecture) claims Merom as an instance of it methinks there is more evidence against such an assertion. I do agree that there was much confusion in naming such things in the past (likely when that article was written) even within Intel.50.53.15.59 (talk)23:42, 23 July 2013 (UTC)[reply]

My565525392 edit has nothing to do withConroe andMerom chips. Open a new section if you want to discuss 565525392.Visite fortuitement prolongée (talk)20:15, 24 July 2013 (UTC)[reply]

Can someone please fix the table? It appears to be messed up. --24.211.245.252 (talk)00:41, 11 April 2014 (UTC)[reply]

What precisely do you find messed up? — Dsimic (talk | contribs)02:01, 13 April 2014 (UTC)[reply]

https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures

Merge should be considered given the breaking of tick/tock with Kaby Lake.— Precedingunsigned comment added by50.254.49.177 (talk)23:07, 16 July 2015 (UTC)[reply]

Done68.165.77.79 (talk)04:27, 23 September 2015 (UTC)[reply]

Here is an article on the future fabrication process atIntel Accelerates Process and Packaging Innovations.Rjluna2 (talk)17:20, 28 July 2021 (UTC)[reply]

There are some Presentation Slides showing the roadmap for forthcoming Intel Xeon microprocessor can be found atIntel Investor Meeting 2022.Rjluna2 (talk)14:30, 22 February 2022 (UTC)[reply]

Here is the Intel'sAI Coming to the PC at Scale.Rjluna2 (talk)15:58, 25 May 2023 (UTC)[reply]

Intel is introducing power circuitry sandwiched between the top and bottom layers for that 20A node process. More information atWith PowerVia, Intel Achieves a Chipmaking Breakthrough.Rjluna2 (talk)18:18, 6 June 2023 (UTC)[reply]

Here is an article fromTom's Hardware/MSN about this forthcoming onIntel Lunar Lake Core Types Seemingly Confirmed by PerfMon.Rjluna2 (talk)11:37, 11 August 2023 (UTC)[reply]

There are several forthcoming group of future processor as discussed atIntel Innovation 2023: Empowering Developers to Bring AI Everywhere.Rjluna2 (talk)20:31, 22 September 2023 (UTC)[reply]

There are several iteration on these forthcoming generation microprocessor as discussed atIntel Innovation 2023 Day 1 Keynote Presentation Slides.Rjluna2 (talk)15:36, 23 September 2023 (UTC)[reply]

Intel Launches Intel Core 14th Gen Desktop Processors for Enthusiasts, but it uses the7-nm process technology.Rjluna2 (talk)16:13, 16 October 2023 (UTC)[reply]

Bob Brennan explains the 18A process for the Intel Xeon processor code-named Clearwater Forest atRedefining the Foundry for an Era of AI.Rjluna2 (talk)17:26, 20 March 2024 (UTC)[reply]

Here is an article that contains information on Intel Xeon 6 and forthcoming Lunar Lake microprocessor atIntel Unleashes Enterprise AI with Gaudi 3, AI Open Systems Strategy and New Customer Wins.Rjluna2 (talk)15:33, 11 April 2024 (UTC)[reply]

According to phd ian cutress 4nm was a limited version of 3nm which couldn't do general purpose circuits but could do io, 3nm wasn't a shrink but rather the general purpose release of 4nm, with the same being true of 2nm and 18a where 2nm was a pre-production version of 18a.https://youtube.com/live/acUSa01BPEcFanccr (talk)22:32, 17 October 2024 (UTC)[reply]

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