The SuperSPARC microprocessor | |
| General information | |
|---|---|
| Launched | 1992 |
| Discontinued | 1995 |
| Designed by | Sun Microsystems |
| Common manufacturer | |
| Performance | |
| Max.CPUclock rate | 33 MHz to 90 MHz |
| Physical specifications | |
| Transistors |
|
| Cores |
|
| Cache | |
| L2 cache | none, 1 MB, 2 MB |
| Architecture and classification | |
| Instruction set | SPARC V8 |
TheSuperSPARC is amicroprocessor that implements theSPARC V8instruction set architecture (ISA) developed bySun Microsystems. 33 and 40 MHz versions were introduced in 1992. The SuperSPARC contains 3.1 million transistors. It was fabricated byTexas Instruments (TI) at Miho, Japan in a 0.8 micrometre triple-metal[1]BiCMOS process.[2]
There are two derivatives of the SuperSPARC: the SuperSPARC+ and SuperSPARC-II. The SuperSPARC+ was developed to remedy some of the design flaws that limited the SuperSPARC's clock frequency and thus performance. The SuperSPARC-II, introduced in 1994, was a major revision with improvements that enabled the microprocessor to reach 85 MHz in desktop systems and 90 MHz in the more heavily cooled SPARCserver-1000E.
SuperSPARC CPU modules are used in both theSPARCstation 10 andSPARCstation 20.
The SuperSPARC-II was replaced in 1995 by the 64-bitUltraSPARC, an implementation of the64-bitSPARC V9 ISA.
| Model | CPU | L2 Cache | Clock Speed | Bus Speed | Notes |
|---|---|---|---|---|---|
| SM20 | 1 CPU | none | 33 MHz | 33 MHz | |
| SM21 | 1 CPU | 1 MB | 33 MHz | 33 MHz | only works in early SPARCserver-2000 systems |
| SM30 | 1 CPU | none | 36 MHz | 36 MHz | |
| SM40 | 1 CPU | none | 40 MHz | 40 MHz | |
| SM41 | 1 CPU | 1 MB | 40.3 MHz | 40 MHz | |
| SM50 | 1 CPU | none | 50 MHz | 50 MHz | |
| SM51 | 1 CPU | 1 MB | 50 MHz | 40 MHz | |
| SM51-2 | 1 CPU | 2 MB | 50 MHz | 40 MHz | |
| SM52 | 2 CPU | 1 MB | 45 MHz | 40 MHz | |
| SM52X | 2 CPU | 1 MB | 50 MHz | 40 MHz | |
| SM61 | 1 CPU | 1 MB | 60 MHz | 50/55 MHz | |
| SM61-2 | 1 CPU | 2 MB | 60 MHz | 50/55 MHz |
| Model | CPU | L2 Cache | Clock Speed | Bus Speed | Notes |
|---|---|---|---|---|---|
| SM71 | 1 CPU | 1 MB | 75 MHz | 50 MHz | |
| SM81 | 1 CPU | 1 MB | 85 MHz | 50 MHz | |
| SM81-2 | 1 CPU | 2 MB | 85 MHz | 50/55 MHz | |
| SM91-2 | 1 CPU | 2 MB | 90 MHz | 50 MHz |
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