AMD Steamroller Family 15h is amicroarchitecture developed byAMD forAMD APUs, which succeededPiledriver in the beginning of 2014 as the third-generationBulldozer-based microarchitecture.^[2] Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism.

Steamroller still features two-core modules found inBulldozer andPiledriver designs calledclustered multi-thread (CMT), meaning that one module is marketed as a dual-core processor.^[3] The focus ofSteamroller is for greater parallelism.^[4] Improvements center on independent instruction decoders for each core within a module, 25% more of the maximum width dispatches per thread, better instruction schedulers, improved perceptron branch predictor, larger and smarter caches, up to 30% fewer instruction cache misses, branch misprediction rate reduced by 20%, dynamically resizable L2 cache, micro-operations queue,^[5] more internal register resources and improved memory controller.

AMD estimated that these improvements will increaseinstructions per cycle (IPC) up to 30% compared to the first-generation Bulldozer core while maintaining Piledriver's high clock rates with decreased power consumption.^[3] The final result was a 9% single-threaded IPC improvement, and 18% multi-threaded IPC improvement over Piledriver.^[6]

Steamroller, the microarchitecture for CPUs, as well asGraphics Core Next, the microarchitecture for GPUs, are paired together in the APU lines to support features specified inHeterogeneous System Architecture.

In 2011, AMD announced a third-generation Bulldozer-based line of processors for 2013,^[7] withNext Generation Bulldozer as the working title, using the 28 nm manufacturing process.^[8]

On 21 September 2011, leaked AMD slides indicated that this third generation of Bulldozer core was codenamedSteamroller.^[9][10]

In January 2014, the firstKaveri APUs became available.^[11]

Starting from May 2015 till March 2016 new APUs were launched as Kaveri-refresh (codenamed Godavari).^[12]

The following table shows features ofAMD's processors with 3D graphics, includingAPUs (see also:List of AMD processors with 3D graphics).

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló			Phoenix
		Entry																				Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle,Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPUmicroarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"[13]	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+[14]	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	—												AM5	—	—
		Mainstream	—					AM4						—		—
		Entry	FM1	FM2		FM2+		FM2+[a],AM4	AM4					—
		Basic	—														—	AM1	—			FP5	—
	Other		FS1	FS1+,FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			—														—
Fab. (nm)			GF32SHP (HKMGSOI)			GF28SHP (HKMG bulk)				GF14LPP (FinFET bulk)	GF12LP (FinFET bulk)	TSMCN7 (FinFET bulk)		TSMCN6 (FinFET bulk)	CCD: TSMCN5 (FinFET bulk) cIOD: TSMCN6 (FinFET bulk)	TSMC4nm (FinFET bulk)	TSMCN40 (bulk)	TSMCN28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF14LPP (FinFET bulk)		GF12LP (FinFET bulk)	TSMCN6 (FinFET bulk)
Die area (mm2)			228	246		245		245	250	210[15]		156	180	210	CCD: (2x) 70 cIOD: 122	178	75(+ 28FCH)	107		?	125	149			~100
MinTDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APUTDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node[b]			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
MaxCPU[c]cores per APU			4									8			16	8	2	4			2			4
Maxthreads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686,PAE,NX bit, CMPXCHG16B,AMD-V,RVI,ABM, and 64-bit LAHF/SAHF
IOMMU[d]			—	v2													v1		v2
BMI1,AES-NI,CLMUL, andF16C																	—
MOVBE			—
AVIC,BMI2,RDRAND, and MWAITX/MONITORX																	—
SME[e],TSME[e],ADX,SHA,RDSEED,SMAP,SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—														—
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—														—
MPK,VAES			—														—
SGX			—														—
FPUs percore			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPUinstruction setSIMD level			SSE4a[f]	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	—													—
PREFETCH/PREFETCHW
GFNI			—														—
AMX			—
FMA4, LWP,TBM, andXOP			—							—							—					—
FMA3
AMD XDNA			—														—
L1 data cache per core (KiB)			64	16				32									32
L1 data cacheassociativity (ways)			2	4				8									8
L1 instruction caches percore			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cacheassociativity (ways)			2			3				4		8					2				3	4			8
L2 caches percore			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cacheassociativity (ways)			16							8							16					8
Max on-dieL3 cache per CCX (MiB)			—							4			16		32		—						4
Max 3D V-Cache per CCD (MiB)										—					64	—							—
Max total in-CCDL3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										—					64	—							—
Max. boardL3 cache per APU (MiB)										—													—
Max totalL3 cache per APU (MiB)										4		8	16		128								4
APU L3 cacheassociativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max.L4 cache			—														—
Max stockDRAM support			DDR3-1866		DDR3-2133			DDR3-2133,DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200,LPDDR4-4266		DDR5-4800,LPDDR5-6400	DDR5-5200	DDR5-5600,LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866,DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
MaxDRAM channels per APU			2														1					2	1	2
Max stockDRAMbandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPUmicroarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen[16]				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen[16]	GCN 5th gen			RDNA 2
GPUinstruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU baseGFLOPS[g]			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine[h]			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16[17]		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0[18]		VCN 2.1[19]	VCN 2.2[19]	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			—	VCE 1.0		VCE 2.0		VCE 3.1									—	VCE 2.0			VCE 3.4
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune													PowerPlay	PowerTune[20]
TrueAudio			—			[21]							?				—
FreeSync						1 2												1 2
HDCP[i]			?			1.4				2.2				2.3			?	1.4				2.2			2.3
PlayReady[i]			—							3.0 not yet							—					3.0 not yet
Supported displays[j]			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4					2				3	4		4
/drm/radeon[k][23][24]									—												—
/drm/amdgpu[k][25]			—			[26]											—	[26]

1. Kaveri A-series APU
   • Desktop budget and mainstream markets (FM2+): TheTrinity /Richland APU line was replaced in January 2014 by theKaveri APU line, as the third generation of A10, A8, A6 and A4 series for the desktop market. Top-of-the-line model in 2014 was the quad-core A10-7850K APU, with a 3.7 GHz core frequency and 4 MB L2 cache, incorporating a 720 MHz GPU with 512 stream processors and over 856GFLOPS of totalprocessing power.^[27]
     In 2015 and 2016 new models with two to four enhancedSteamroller B cores were released as Kaveri-refresh / Godavari. A10-7890K, the new top-of-the-line model, features an increased core frequency of 4.1 GHz and an 866 MHz GPU.
   • Two or four CPU cores based on the Steamroller microarchitecture
   • Socket FM2+-only, Socket FM2 isnot supported,^[28] support forPCIe 3.0
   • DDR3 Dual-channel (2x64-bit) memory controller
   • AMD Heterogeneous System Architecture (HSA) 2.0
   • SIP blocks:Unified Video Decoder,Video Coding Engine,TrueAudio^[29]
   • Three to eight Compute Units (CUs) based on the revisedGCN 2nd gen microarchitecture;^[30] 1 Compute Unit (CU) consists of 64Unified Shader Processors : 4Texture Mapping Units (TMUs) : 1Render Output Unit (ROP)
   • AMD Eyefinity up to 4 monitors,^[31] 4K Ultra HD support, DisplayPort 1.2 Support^[32]
   • Select models supportAMD Hybrid Graphics by using a Radeon R7 240 or R7 250 discrete graphics card.^[33]
   • Integrated customARM Cortex-A5 co-processor^[34] withTrustZone Security Extensions^[35]
2. Berlin APU - canceled
   • Announced in 2013 by AMD^[36] theBerlin APU were targeted at the enterprise and server markets featuring fourSteamroller cores, up to 512 stream processors and support forECC memory.

In November 2013 AMD confirmed it would not update theFX series in 2014, neither itsSocket AM3+ version, nor will it receive aSteamroller version with a new socket.^[37][38]

AMD however, released a Kaveri based FX-770K for desktop and FX-7600P for mobile which are basically APUs with their integrated graphics disabled similar to the Athlon X4 FM2+ line. Those APUs were released for OEMs only.

AMD's server roadmaps for 2014 showed:^[39][40]

• Berlin APU - quad-core x86 Steamroller architecture (as described above) for 1 Processor (1P) compute and media clusters
• Berlin CPU - quad-core x86 Steamroller architecture for 1P web and enterprise services clusters
• Seattle CPU - 4/8 coreAArch64Cortex-A57 architecture (Opteron A1100) for 1P web and enterprise services clusters^[41]
• Warsaw CPU - up to 16 corex86Piledriver (2nd gen Bulldozer) architecture (Opteron 6338P and 6370P) for 2P/4P servers^[42]

However, plans forSteamroller Opteron products were cancelled, likely due to the poorenergy efficiency achieved in this generation of theBulldozer architecture. Energy efficiency was greatly increased in the following generation,Excavator, which exceededJaguar in performance per watt, and approximately doubled performance/watt overSteamroller (for example 20.74 pt/W vs 10.85 pt/W when comparing similar mobile APUs using rough arbitrary metrics).^[43][44]

• AMD x86 microprocessors
• AMD microarchitectures
• Heterogeneous System Architecture
• X86 microarchitectures

• Articles with short description
• Short description is different from Wikidata