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Incomputing, abus error is afault raised by hardware, notifying anoperating system (OS) that a process is trying to accessmemory that theCPU cannot physically address: an invalid address for theaddress bus, hence the name. In modern use on most architectures these are much rarer thansegmentation faults, which occur primarily due to memory access violations: problems in thelogical address or permissions.
OnPOSIX-compliant platforms, bus errors usually result in the SIGBUS signal being sent to the process that caused the error. SIGBUS can also be caused by any general device fault that the computer detects, though a bus error rarely means that thecomputer hardware is physically broken—it is normally caused by abug insoftware.[citation needed] Bus errors may also be raised for certain other paging errors; see below.
There are at least three main causes of bus errors:
Software instructs the CPU to read or write a specific physicalmemory address. Accordingly, the CPU sets this physical address on itsaddress bus and requests all other hardware connected to the CPU to respond with the results, if they answer for this specific address. If no other hardware responds, the CPU raises anexception, stating that the requested physical address is unrecognized by the whole computer system. Note that this only coversphysical memory addresses. Trying to access an undefinedvirtual memory address is generally considered to be a segmentation fault rather than a bus error, though if theMMU is separate, the processor cannot tell the difference.
Most CPUs arebyte-addressable, where each unique memory address refers to an 8-bitbyte. Most CPUs can access individual bytes from each memory address, but they generally cannot access larger units (16 bits, 32 bits, 64 bits and so on) without these units being "aligned" to a specific boundary (thex86 platform being a notable exception).
For example, if multi-byte accesses must be 16 bit-aligned, addresses (given in bytes) at 0, 2, 4, 6, and so on would be considered aligned and therefore accessible, while addresses 1, 3, 5, and so on would be considered unaligned. Similarly, if multi-byte accesses must be 32-bit aligned, addresses 0, 4, 8, 12, and so on would be considered aligned and therefore accessible, and all addresses in between would be considered unaligned. Attempting to access a unit larger than a byte at an unaligned address can cause a bus error.
Some systems may have a hybrid of these depending on the architecture being used. For example, for hardware based on theIBM System/360 mainframe, including theIBM System z, Fujitsu B8000, RCA Spectra, andUNIVAC Series 90, instructions must be on a 16-bit boundary, that is, execution addresses must start on an even byte. Attempts to branch to an odd address results in a specification exception.[1] Data, however, may be retrieved from any address in memory, and may be one byte or longer depending on the instruction.
CPUs generally access data at the full width of theirdata bus at all times. To address bytes, they access memory at the full width of their data bus, then mask and shift to address the individual byte. Systems tolerate this inefficient algorithm, as it is an essential feature for most software, especiallystring processing. Unlike bytes, larger units can span two aligned addresses and would thus require more than one fetch on the data bus.It is possible for CPUs to support this, but this functionality is rarely required directly at themachine code level, thus CPU designers normally avoid implementing it and instead issue bus errors for unaligned memory access.
FreeBSD,Linux andSolaris can signal a bus error when virtual memory pages cannot bepaged in, e.g. because it has disappeared (e.g. accessing amemory-mapped file or executing abinary image which has been truncated while the program was running),[2][unreliable source?] or because a just-createdmemory-mapped file cannot be physically allocated, because the disk is full.
Onx86 there exists an older memory management mechanism known assegmentation.If the application loads a segment register with the selector of a non-present segment (which under POSIX-compliant OSescan only be done withassembly language), the exceptionis generated. Some OSes used that for swapping, but under Linux this generates SIGBUS.
This is an example of unaligned memory access, written in theC programming language withAT&T assembly syntax.
#include<stdlib.h>intmain(intargc,char**argv){int*iptr;char*cptr;#if defined(__GNUC__)# if defined(__i386__)/* Enable Alignment Checking on x86 */__asm__("pushf\norl $0x40000,(%esp)\npopf");# elif defined(__x86_64__)/* Enable Alignment Checking on x86_64 */__asm__("pushf\norl $0x40000,(%rsp)\npopf");# endif#endif/* malloc() always provides memory which is aligned for all fundamental types */cptr=malloc(sizeof(int)+1);/* Increment the pointer by one, making it misaligned */iptr=(int*)++cptr;/* Dereference it as an int pointer, causing an unaligned access */*iptr=42;/* Following accesses will also result in sigbus error. short *sptr; int i; sptr = (short *)&i; // For all odd value increments, it will result in sigbus. sptr = (short *)(((char *)sptr) + 1); *sptr = 100; */return0;}
Compiling and running the example on aPOSIX compliant OS onx86 demonstrates the error:
$gcc-ansisigbus.c-osigbus$./sigbusBus error$gdb./sigbus(gdb)rProgram received signal SIGBUS, Bus error.0x080483ba in main ()(gdb)x/i $pc0x80483ba <main+54>: mov DWORD PTR [eax],0x2a(gdb)p/x $eax$1=0x804a009(gdb)p/t $eax & (sizeof(int) - 1)$2=1
TheGDBdebugger shows that theimmediate value 0x2a is being stored at the location stored in theEAXregister, usingX86 assembly language. This is an example ofregister indirect addressing.
Printing thelow order bits of the address shows that it is notaligned to a word boundary ("dword" using x86 terminology).