ASHA instruction set is a set of extensions to theARM,RISC-V andx86instruction set architecture which supporthardware acceleration of theSecure Hash Algorithm (SHA) family.

SHA-1 andSHA-256 instructions appeared as optional features (FEAT_SHA1 and FEAT_SHA256) in the Arm V8.0 architecture introduced in 2011.^[1] The instructions are:

• SHA-1:SHA1C,SHA1H,SHA1M,SHA1P,SHA1SU0,SHA1SU1
• SHA-256:SHA256H,SHA256H2,SHA256SU0,SHA256SU1

SHA-512 and SHA-3 instructions appeared as optional features (FEAT_SHA512 and FEAT_SHA3) in the Arm V8.2 architecture.^[2] The instructions are:

• SHA-512:SHA512H,SHA512H2,SHA512SU0,SHA512SU1
• SHA-3:EOR3,RAX1,XAR,BCAX

A scalable vector extension (SVE) version of the SHA-3 instructions appeared as an optional feature (FEAT_SVE_SHA3) in the Arm V9.0 architecture.^[3]

SHA2 instructions are part of the Zknh extension part of theRISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions ratified in November 2021^[4].

The originalSSE-based extensions added four instructions supportingSHA-1 and three forSHA-256 and were specified in 2013 by Intel.^[5] Instructions forSHA-512 was introduced inArrow Lake andLunar Lake in 2024..

• SHA-1:SHA1RNDS4,SHA1NEXTE,SHA1MSG1,SHA1MSG2
• SHA-256:SHA256RNDS2,SHA256MSG1,SHA256MSG2

The newer SHA-512 instruction set comprisesAVX-based versions of the original SHAinstruction set marked with aV prefix and these three new AVX-based instructions forSHA-512:

• VSHA512RNDS2,VSHA512MSG1,VSHA512MSG2

All recent AMD processors support the original SHA instruction set:

• AMDZen^[6] (2017) and later processors.

The following Intel processors support the original SHA instruction set:

• IntelGoldmont^[7] (2016) and later Atom microarchitecture processors.
• IntelCannon Lake^[8] (2018/2019),Ice Lake^[9] (2019) and later processors for laptops ("mainstream mobile").
• IntelRocket Lake (2021) and later processors for desktop computers.

The following Intel processors will support the newer SHA-512 instruction set:

• IntelArrow Lake andLunar Lake processors.

• Chapter 8 of"Intel Architecture Instruction Set Extensions Programming Reference"(PDF). Archived fromthe original(PDF) on 2013-09-29.

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