 A prototype version of a Shakti microcontroller. | |
| General information | |
|---|---|
| Designed by | Indian Institute of Technology, Madras |
| Common manufacturers | |
| Architecture and classification | |
| Application | SoC, development boards, based software platform, IOT |
| Instruction set | RISC-V |
| Models |
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Shakti (stylized asSHAKTI) is anopen-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group atIIT Madras to develop the first indigenous industrial-grade processor.[1][2] The aims of the Shakti initiative include building anopen source production-grade processor, completesystems on a chip,microprocessor development boards, and a Shakti-basedsoftware platform. The main focus of the team iscomputer architecture research to develop SoCs, which are competitive with commercial offerings in the market in area, power, and performance. Thesource code for Shakti isopen-sourced under theModified BSD License.[3][2]
V. Kamakoti carried out the SHAKTI Microprocessor Project, at Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture (Department of Computer Science & Engineering, IIT Madras). TheMinistry of Electronics and Information Technology supports it through its Digital India RISC-V initiative.[4]
Shakti processors are based on theRISC-Vinstruction set architecture (ISA). The processors are designed to have either22 nm processfin field-effect transistor (FinFET) or180 nm process complementary metal–oxide–semiconductor (CMOS) technology nodes depending on the manufacturingsemiconductor fabrication plant (foundry).
Shakti plans a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".
The E and C-classes core are for theInternet of things (IoT),embedded system, anddesktop computer markets. The processor design is free of any royalty and isopen-source licensed under the modifiedBSD License.[5]
E-class and C-class cores are both implemented inBluespecSystemVerilog (BSV) language, aHaskell dialect.[2]
The Shakti project aims to build 6 variants of processors based on the RISC-V ISA.
The E-class are32- and64-bitmicrocontrollers able to support all extensions of the RISC-V ISA, for low-power and low computer applications. The E-class is an in-order 3 stagepipeline having an operational frequency of less than 200 MHz on silicon. It is positioned againstARM's M-class (Cortex-M series) cores. It can runreal-time operating systems likeFreeRTOS,Zephyr, and eChronos. Market segments of E-class processor supportsmart cards, IoT devices, motor controls, and robotic platforms.[6][7]
E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip32-bit E-class microcontroller with 128kB RAM. It has 32general-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), aplatform level interrupt controller (PLIC), a Counter, 2Serial Peripheral Interface (SPI), 2universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I²C), 6pulse-width modulator (PWM) and an inbuilt Xilinxanalog-to-digital converter (X-ADC).[8]
The C-class is a64-bit controller class of processor, for mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems likeLinux andSel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It is for mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.[6][7]
C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I²C). It is for mid-range application workloads with a very low power use and support for optional memory protection.[9]
The I-class is a 64-bit processor for the compute, mobile, storage, and networking platforms. Its features includeout-of-order execution,multithreading, aggressivebranch prediction,non-blocking caches and deepinstruction pipelining stages. The operational clock frequency of this processor is 1.5-2.5 GHz. As of April 2020, the team was working on implementing atomics, memory dependence prediction, instruction window/scheduler optimizations, implementation of some functional units, performance analysis/projections, optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.[7][10][11]
A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are for general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance goals.[10]
The S-Class is a 64-bitsuperscalar,multi-threaded variant for desktop and enterprise server uses. Its supports 2–16 cores with a clock frequency of about 1.2–3 GHz.[10]
The H-class is a 64-bit processor for highly parallel enterprise, HPC, and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.[10]
These are experimental/research projects which focus on developing a high security and fault tolerant processor.
The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.[12]
The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.[13]
Two C-class processors (codenamedRIMO andRisecreek) and one E-class processor (Moushik) have beentaped-out so far.
RIMO is the code name of the Shakti C-class based SoC that has been taped-out atSemi-Conductor Laboratory at Mohali using180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP).[6]
CREEK is the code name of the Shakti C-class based SoC that has been taped-out atIntel's Oregon fab using a 22nm FinFET process. The 16mm² chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA).[6]
Moushik is the code name of the Shakti E-class based SoC that has been taped-out at SCL using 180 nm process technology. It operates in frequency of 100 MHz and developed along with a motherboard called Ardonyx 1.0.[14]
IIT Madras andISRO Inertial Systems Unit successfully designed and booted a 64-bit IRIS (Indigenous RISC-V Controller for Space Applications) chip based on the SHAKTI baseline processor in February 2025.[15] The chip configuration takes into account the processing power and functional needs of the devices and sensors utilized in ISRO missions. To improve dependability, fault-tolerant internal memory were interfaced with the SHAKTI core.[16]
IRIS is the third chip produced bySCL using 180 nm process, following RIMO in 2018 and MOUSHIK in 2020. The chip packaging process was handled byTata Advanced Systems. Syrma SGS finished the installation and assembly, while PCB Power developed the motherboard. Chip design, fabrication, packaging, motherboard design and fabrication, software, and boot were all completed in India validating the presence of expertise and complete semiconductor ecosystem. To validate chip performance, a flight test is scheduled.[17][18]
Some of the features of RIMO and Risecreek are as follows:
There are development boards for both E and C-class of processors. The details on the board support for different classes of processors are given below.
Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers.[19]
On December 7, 2021, the Ministry of Electronics and Information Technology honored the Swadeshi Microprocessor Challenge winners. At different phases of the challenge, participants get up to ₹4.40crore in funding for the development of a hardware prototype and the incubation of a start-up by participating teams. C-DAC andIIT Madras made accessible for the challenge their SoCs,THEJAS32 and THEJAS64, based on VEGA 32-bit and 64-bit processors and Shakti. The participating teams successfully implemented the SoCs in a variety of designs. Ten teams became victorious from the 30 finalist teams. Team VEGA FCS FT (AI drone), received a₹35 lakh cheque for their drone application; second-place winners, Team HWDL, received ₹30 lakh for FM Radio Data System Utilities; and third-place winners, Cytox, received ₹25 lakh for theircell count project. Each of the other teams received a check for ₹20 lakh for sharing fourth place. The teams are Astrek Innovations (lower limbexosuit fordisabled), Team 6E Resources (remote monitoring and optimization ofsewage treatment plant), Team Anshashodhak (unique calibration system fornuclear spectroscopy applications), Team Quicproc (wireless maternal monitoring system), Team Avrio Energy (AI Energy Meter with intelligence at edge anddeep learning), and Team JayHawks (anti-theftgeofencing based locking system).[20][21]
Thirty finalist teams of the Swadeshi Microprocessor Challenge have been awarded incubation support by Maker Village, the largest electronic system design and production center in India.[22]
VEGA Series - RISC-V processor developed byCentre for Development of Advanced Computing