| RISC-V assembly language | |
|---|---|
 | |
| Filename extension | .s |
| Developed by | RISC-V Foundation |
| Type of format | Assembly language |
| Open format? | Yes |
| Free format? | Yes |
| Website | riscv |
RISC-V assembly language is alow-level programming language that is used to produceobject code for theRISC-V class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware.
Assemblers includeGNU Assembler andLLVM.
Reserved keywords of RISC-V assembly language.
Each instruction in the RISC-V assembly language is represented by amnemonic which often combines with one or more operands to translate into one or more bytes known as anopcode.
RISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers.
RISC-V instructions use variable-length encoding.
Extensions:
RISC-V assembly language includes instructions for afloating-point unit (FPU).
These largely perform the same operation in parallel on many values.
The RISC-V assembly has conditional branch instructions based on comparison:beq (equal),bne (not equal),blt (less than, signed),bltu (less than, unsigned),bge (greater than or equal, signed), andbgeu (greater than or equal, unsigned).
.section.text.globl_start_start:luia1,%hi(msg)# load msg(hi)addia1,a1,%lo(msg)# load msg(lo)jalrra,puts2:j2b.section.rodatamsg:.string"Hello World\n"
