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Aprogram counter (PC)[1] is aregister that stores where acomputer program is being executed by aprocessor.[2] It is also commonly called theinstruction pointer (IP) inIntelx86 andItaniummicroprocessors, and sometimes called theinstruction address register (IAR),[3][1] theinstruction counter,[4] or just part of the instruction sequencer.[5]
Usually, a PC stores thememory address of aninstruction. Further, it usually is incremented after fetching an instruction, and thereforepoints to the next instruction to be executed.[6] For a processor that increments before fetch, the PC points to the instruction being executed. In some processors, the PC points some distance beyond the current instruction. For instance, in theARM7, the value of PC visible to the programmer reflects instruction prefetching and reads as the address of the current instruction plus 8 in ARM State, or plus 4 in Thumb State.[7] For modern processors, the location of execution in the program is complicated byinstruction-level parallelism andout-of-order execution.
By default, a processor fetches instructions sequentially frommemory, but a control transfer instruction changes the sequence by writing a value in the PC. Abranch allows the next instruction to be fetched from elsewhere in memory. Afunction call not only branches but saves the value of the PC. Areturn restores the value of the PC to resume execution with the instruction following the call by branching to the saved value. A transfer that is conditional on the truth of some condition lets the computer follow a different sequence under different conditions.
In a simplecentral processing unit (CPU), the PC is adigital counter (which is the origin of the term "program counter") that may be one of several hardwareregisters. Theinstruction cycle[8] begins with afetch, in which the CPU places the value of the PC on theaddress bus to send it to the memory. The memory responds by sending the contents of that memory location on thedata bus. (This is thestored-program computer model, in which a single memory space contains both executable instructions and ordinary data.[9]) Following the fetch, the CPU proceeds toexecution, taking some action based on the memory contents that it obtained. At some point in this cycle, the PC will be modified so that the next instruction executed is a different one (typically, incremented so that the next instruction is the one starting at the memory address immediately following the last memory location of the current instruction).
Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC.[10] The number of bits (the width of the PC) relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 232 units of memory. On some processors, the width of the program counter instead depends on the addressable memory; for example, someAVR microcontrollers have a PC which wraps around after 12 bits.[11]
If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the PC by a pulse to its LOAD input.[12]
To identify the current instruction, the PC may be combined with other registers that identify asegment orpage. This approach permits a PC with fewer bits by assuming that most memory units of interest are within the current vicinity.
Use of a PC that normally increments assumes that what a computer does is execute a usually linear sequence of instructions. Such a PC is central to thevon Neumann architecture. Thus programmers write a sequentialcontrol flow even for algorithms that do not have to be sequential. The resulting “von Neumann bottleneck” led to research intoparallel computing,[13] including non-von Neumann ordataflow models that did not use a PC; for example, rather than specifying sequential steps, the high-level programmer might specify desiredfunction and the low-level programmer might specify this usingcombinatory logic.
This research also led to ways to making conventional, PC-based, CPUs run faster, including:
Modern high-levelprogramming languages still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which the programmer's finger identifies the point of execution as a PC would. The high-level language is essentially the machine language of a virtual machine,[14] too complex to be built as hardware but instead emulated orinterpreted by software.
However, new programming models transcend sequential-execution programming:
Program Counter (PC) is a register that keeps track of the program sequence, by storing the address of the instruction currently being executed. It is automatically loaded with zero when the chip is powered up or reset. As each instruction is executed, PC is incremented (increased by one) to point to the next instruction.
3.2.12. WRAPMODE […] AS will assume that the processor's program counter does not have the full length of 16 bits given by the architecture, but instead a length that is exactly sufficient to address the internal ROM. For example, in case of theAT90S8515, this means 12 bits, corresponding to 4 Kwords or 8 Kbytes. This assumption allows relative branches from the ROM's beginning to the end and vice versa which would result in an out-of-branch error when using strict arithmetics. Here, they work because the carry bits resulting from the target address computation are discarded. […] In case of the abovementioned AT90S8515, this option is even necessary because it is the only way to perform a direct jump through the complete address space […]