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Process–architecture–optimization is a development model forcentral processing units (CPUs) thatIntel adopted in 2016. Under this three-phase (three-year) model, everymicroprocessordie shrink is followed by amicroarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year)tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.[1][2][3][4][5]
| Wave[6] | Process (die shrink) | Architecture | Optimizations | Optional backport[7][8] | ||||
|---|---|---|---|---|---|---|---|---|
| 1: 14 nm | 2014: Broadwell (5th gen) | 2015: Skylake (6th gen) | 2016: Kaby Lake (7th gen) | 2017: Coffee Lake (8th gen) | 2018: Coffee Lake Refresh (9th gen) | 2019: Comet Lake (10th gen) | N/A | 2021: Rocket Lake (11th gen,Cypress Cove) |
| References:[1][3][6][9] | ||||||||
| 2: 10 nm (Intel 7) | 2018:[note 1] Cannon Lake (8th gen,Palm Cove) | 2019: Ice Lake (10th gen,Sunny Cove) | 2020: Tiger Lake (11th gen,Willow Cove) | 2021: Alder Lake (12th gen,Golden Cove) | 2022: Raptor Lake (13th gen) | 2023: Raptor Lake Refresh (14th gen) | 2025: Raptor Lake Refresh (Core 200) | N/A |
| References:[1][10][9][11][12] | ||||||||
| 3: Intel 4 & Intel 3 | 2023: Meteor Lake (14th gen) | 2025: Arrow Lake-U (Ultra 200U) | ||||||
| References:[13] | ||||||||
| 3: Intel 20A? & Intel 18A | 2025: Panther Lake (Ultra 300) | 2026?: Nova Lake (Ultra 400?) | ||||||
| References: | ||||||||
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