ThePlatform Controller Hub (PCH) is a family ofIntel's single-chipchipsets, first introduced in 2009. It is the successor to theIntel Hub Architecture, which used two chips–anorthbridge andsouthbridge, and first appeared in theIntel 5 Series.
The PCH controls certain data paths and support functions used in conjunction with IntelCPUs. These include clocking (thesystem clock),Flexible Display Interface (FDI) andDirect Media Interface (DMI), although FDI is used only when the chipset is required to support a processor withintegrated graphics. As such, I/O functions are reassigned between this new central hub and the CPU compared to the previous architecture: some northbridge functions, the memory controller andPCIe lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.AMD has its equivalent for the PCH, known simply as a chipset since the release of theZen architecture in 2017.[1] AMD no longer uses its equivalent for the PCH, theFusion controller hub (FCH).
The PCH architecture supersedes Intel's previousHub Architecture, with its design addressing the eventual problematic performance bottleneck between the processor and themotherboard. Under the Hub Architecture, a motherboard would have a two-piece chipset consisting of a northbridge chip and a southbridge chip. Over time, the speed of CPUs kept increasing but the bandwidth of thefront-side bus (FSB) (connection between the CPU and the motherboard) did not, resulting in a performance bottleneck.[2]
As a solution to the bottleneck, several functions belonging to the traditionalnorthbridge andsouthbridge chipsets were rearranged. The northbridge and its functions are now eliminated completely: The memory controller, PCI Express lanes forexpansion cards and other northbridge functions are now incorporated into the CPU die as asystem agent (Intel) or packaged in the processor on an I/O die (AMD Zen 2).
The PCH then incorporates a few of the remaining northbridge functions (e.g. clocking) in addition to all of the southbridge's functions, replacing it. The system clock was previously a connection to a dedicated chip but is now incorporated into the PCH. Two different connections exist between the PCH and the CPU:Flexible Display Interface (FDI) andDirect Media Interface (DMI). The FDI is used only when the chipset requires supporting a processor with integrated graphics. TheIntel Management Engine was also moved to the PCH starting with theNehalem processors and5-Series chipsets. AMD's chipsets instead use several PCIe lanes to connect with the CPU while also providing their own PCIe lanes, which are also provided by the processor itself.[3][4] The chipset also contains theNonvolatile BIOS memory.
With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets is now relieved.
This style began inNehalem and will remain for the foreseeable future, throughCannon Lake.
Beginning with ultra-low-powerHaswells and continuing with mobileSkylake processors, Intel incorporated the southbridge IO controllers into the CPU package, eliminating the PCH for asystem in package (SOP) design with two dies; the larger die being the CPU die, the smaller die being the PCH die.[5] Rather thanDMI, these SOPs directly expose PCIe lanes, as well as SATA, USB, andHDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, andSMBus lines. However, afully integrated voltage regulator will be absent until Cannon Lake.[needs update]
AMD's FCH has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.[6] However, since the release of the Zen architecture, there's still a component called a chipset which only handles relatively low speed I/O such as USB and SATA ports and connects to the CPU with a PCIe connection. In these systems all PCIe connections are routed directly to the CPU.[7] The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I/O.[8]AMD server and laptop CPUs adopt a self containedsystem on chip (SoC) design instead which doesn't require a chipset.[9][10][11]
TheIntel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamedIbex Peak.
This has the following variations:
Langwell is the codename of a PCH in theMoorestownMID/smartphone platform.[12][13] forAtomLincroft microprocessors.
This has the following variations:
Tiger Point is the codename of a PCH in thePine Trail netbook platform chipset forAtomPineview microprocessors.
This has the following variations:
Topcliff is the codename of a PCH in theQueens Bay embedded platform chipset forAtomTunnel Creek microprocessors.
It connects to the processor via PCIe (vs.DMI as other PCHs do).
This has the following variations:
Cougar Point is the codename of a PCH inIntel 6 Series chipsets for mobile, desktop, workstation, and server platforms. It is most closely associated withSandy Bridge processors.
This has the following variations:
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In the first month after Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered. Specifically, a transistor in the 3 Gbit/sPLL clocking tree was receiving too high voltage. The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and optical drives. The bug was present in revision B2 of the chipsets, and was fixed with B3. Z68 did not have this bug, since the B2 revision for it was never released. 6 Gbit/s ports were not affected. This bug was especially a problem with the H61 chipset, which only had 3 Gbit/s SATA ports. ThroughOEMs, Intel plans to repair or replace all affected products at a cost of $700 million.[14][15]
Nearly all produced motherboards using Cougar Point chipsets were designed to handle Sandy Bridge, and later Ivy Bridge, processors.ASRock produced one motherboard forLGA 1156 processors, based on P67 chipset, the P67 Transformer. It exclusively supportsLynnfield Core i5/i7 and Xeon processors, using LGA 1156 socket. After revision B2 of Cougar Point chipsets was recalled, ASRock decided not to update the P67 Transformer motherboard, and was discontinued. Some small Chinese manufacturers are producing LGA 1156 motherboards with H61 chipset.
Whitney Point is the codename of a PCH in theOak Trail tablet platform forAtomLincroft microprocessors.
This has the following variations:
Panther Point is the codename of a PCH inIntel 7 Series chipsets for mobile and desktop. It is most closely associated withIvy Bridge processors. Thesechipsets (except PCH HM75) have integratedUSB 3.0.[16]
This has the following variations:
Cave Creek is the codename of the PCH most closely associated withCrystal Forest platforms andGladden[17] orSandy Bridge-EP/EN[18] processors.
Patsburg is the codename of a PCH inIntel 7 Series chipsets for server and workstation using theLGA 2011 socket. It was initially launched in 2011 as part ofIntel X79 for the desktop enthusiastSandy Bridge-E processors inWaimea Bay platforms.[19] Patsburg was then used for theSandy Bridge-EP server platform (the platform was codenamed Romley and the CPUs codenamed Jaketown, and finally branded asXeon E5-2600 series) launched in early 2012.[20]
Launched in the fall of 2013, theIvy Bridge-E/EP processors (the latter branded as Xeon E5-2600 v2 series) also work with Patsburg, typically with a BIOS update.[21][22]
Patsburg has the following variations:
Coleto Creek is the codename of the PCH most closely associated withHighland Forest platforms andIvy Bridge-EP[23] processors.
Lynx Point is the codename of a PCH inIntel 8 Series chipsets, most closely associated withHaswell processors withLGA 1150 socket.[24] The Lynx Point chipset connects to the processor primarily over theDirect Media Interface (DMI) interface.[25]
The following variants are available:[26]
In addition the following newer variants are available, additionally known asWildcat Point, which also supportHaswell Refresh processors:[27]
A design flaw causes devices connected to the Lynx Point's integratedUSB 3.0 controller to be disconnected when the system wakes up from the S3 state (Suspend to RAM), forcing the USB devices to be reconnected although no data is lost.[28][29] This issue is corrected in C2stepping level of the Lynx Point chipset.[30]
Wellsburg is the codename for the C610-series PCH, supporting theHaswell-E (Core i7 Extreme),Haswell-EP (Xeon E5-16xx v3 andXeon E5-26xx v3), andBroadwell-EP (Xeon E5-26xx v4) processors. Generally similar to Patsburg, Wellsburg consumes only up to 7 W when fully loaded.[31]
Wellsburg has the following variations:
Sunrise Point is the codename of a PCH inIntel 100 Series chipsets, most closely associated withSkylake processors withLGA 1151 socket.
The following variants are available:[32]
Union Point is the codename of a PCH inIntel 200 Series chipsets, most closely associated withKaby Lake processors withLGA 1151 socket.
The following variants are available:[33]
Lewisburg is the codename for the C620-series PCH, supportingLGA 2066 socketedSkylake-X/Kaby Lake-X processors ("Skylake-W" Xeon).
Lewisburg has the following variations:
Basin Falls is the codename for the C400-series PCH, supportingSkylake-X/Kaby Lake-X processors (branded Core i9 Extreme and "Skylake-W" Xeon). Generally similar to Wellsburg, Basin Falls consumes only up to 6 W when fully loaded.
Basin Falls has the following variations:
Cannon Point is the codename of a PCH inIntel 300 Series chipsets, most closely associated withCoffee Lake processors withLGA 1151 socket.[34]
The following variants are available:[35]
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