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Apin grid array (PGA) is a type ofintegrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,[1] and may or may not cover the entire underside of the package. 1.27 mm (0.05") is commonly used with higher pin count PGAs.
PGAs are often mounted onprinted circuit boards using thethrough hole method or inserted into asocket. PGAs allow for more pins per integrated circuit than older packages, such asdual in-line package (DIP).
The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either bywire bonding or throughflip chip mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for exampleZen 2 andZen 3 Ryzen CPUs for theAM4 socket.
Aflip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which thedie faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with theheatsink or other cooling mechanism.
FC-PGA CPUs were introduced byIntel in 1999, for Coppermine corePentium III andCeleron[2] processors based onSocket 370, and were produced untilSocket G3 in 2013. FC-PGA processors fit intozero insertion force (ZIF)motherboard sockets; similar packages were also used by AMD.
A ceramic pin grid array (CPGA) is a type of packaging used byintegrated circuits. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. SomeCPUs that use CPGA packaging are the AMDSocket AAthlons and theDuron.
A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based onSocket AM2 andSocket AM2+. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses aceramic substrate with pins arranged in an array.
An organic pin grid array (OPGA) is a type of connection forintegrated circuits, and especiallyCPUs, where thesilicondie is attached to a plate made out of anorganicplastic which is pierced by an array ofpins which make the requisite connections to thesocket.
Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino coreCeleron processors based onSocket 370.[3] Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.
The staggered pin grid array (SPGA) is used by Intel processors based onSocket 5 andSocket 7.Socket 8 used a partial SPGA layout on half the processor.
It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal squarelattice. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such asmicroprocessors.
A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use insurface-mount technology. The polymer stud grid array or plastic stud grid array was developed jointly by theInteruniversity Microelectronics Centre (IMEC) andLaboratory for Production Technology,Siemens.[4][5]
The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1 mm,[6] as opposed to the 1.27 mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in theG1,G2, andG3 sockets.
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