In the seven-layerOSI model ofcomputer networking, thephysical layer orlayer 1 is the first and lowest layer: the layer most closely associated with the physical connection between devices. The physical layer provides an electrical, mechanical, and procedural interface to the transmission medium. The shapes and properties of theelectrical connectors, the frequencies to transmit on, theline code to use and similar low-level parameters are specified by the physical layer.
The physical layer defines the means of transmitting a stream of rawbits[2] over a physicaldata link connectingnetwork nodes. Thebitstream may be grouped into code words or symbols and converted to a physicalsignal that is transmitted over atransmission medium.
The physical layer consists of theelectronic circuit transmission technologies of a network.[3] It is a fundamental layer underlying the higher level functions in a network, and can be implemented through a great number of different hardware technologies with widely varying characteristics.[4]
Within the semantics of the OSI model, the physical layer translates logical communications requests from thedata link layer into hardware-specific operations to cause transmission or reception of electronic (or other) signals.[5][6] The physical layer supports higher layers responsible for generation of logicaldata packets.
TheInternet protocol suite, as defined inRFC 1122 andRFC 1123, is a high-level networking description used for the Internet and similar networks. It does not define a layer that deals exclusively with hardware-level specifications and interfaces, as this model does not concern itself directly with physical interfaces.[9][10]
Micrel KS8721CL – 3.3 V single power supply 10/100BASE-TX/FX MII physical layer transceiver
TheEthernet PHY is a component that operates at the physical layer of theOSI network model. It implements the physical layer portion of the Ethernet. Its purpose is to provide analog signal physical access to the link. It is usually interfaced with amedia-independent interface (MII) to a MAC chip in amicrocontroller or another system that takes care of the higher layer functions.
More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernetframes; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layerpacket signaling.[17] The PHY usually does not handle MAC addressing, as that is thelink layer's job. Similarly,Wake-on-LAN andBoot ROM functionality is implemented in thenetwork interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.
Common Ethernet interfaces include fiber or two to four copper pairs for data communication. However, there now exists a new interface, called Single Pair Ethernet (SPE), which is able to utilize a single pair of copper wires while still communicating at the intended speeds.Texas Instruments DP83TD510E[18] is an example of a PHY which uses SPE.
Examples include theMicrosemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family,Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers, Texas Instruments DP838xx family[19] and offerings from Intel[20] and ICS.[21]
Wireless LAN orWi-Fi: The PHY portion consists of the RF, mixed-signal and analog portions, which are often called transceivers, and the digital baseband portion that usesdigital signal processor (DSP) and communication algorithm processing, includingchannel codes. It is common that these PHY portions are integrated with themedium access control (MAC) layer insystem-on-a-chip (SOC) implementations. Similar wireless applications include3G/4G/LTE/5G,WiMAX andUWB.
Universal Serial Bus (USB): A PHY chip is integrated into most USB controllers in hosts orembedded systems and provides the bridge between the digital and modulated parts of the interface.
IrDA: TheInfrared Data Association's (IrDA) specification includes an IrPHY specification for the physical layer of the data transport.
Serial ATA (SATA): Serial ATA controllers use a PHY.
PCI Express (PCIe): PCI Express controllers use a PHY.