| Designer | Originally Damjan Lampret, now theOpenRISC Community (Stafford Horne etc.) |
|---|---|
| Bits | 32-bit,64-bit |
| Introduced | 2000; 25 years ago (2000) |
| Version | 1.4[1] |
| Design | RISC |
| Encoding | Fixed |
| Endianness | Big; unimplemented stub for Little |
| Page size | 8 KiB |
| Extensions | ORFPX32/64,[2] ORVDX64[3] |
| Open | Yes (LGPL / GPL), hence royalty free |
| Registers | |
| General-purpose | 16 or 32 |
| Floating-point | Optional |
OpenRISC is a project to develop a series ofopen-source hardware basedcentral processing units (CPUs) on establishedreduced instruction set computer (RISC) principles. It includes aninstruction set architecture (ISA) using anopen-source license. It is the original flagship project of theOpenCores community.
The first (and as of 2019[update] only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of32-bit and64-bit processors with optionalfloating-point arithmetic andvector processing support.[4]TheOpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in theVeriloghardware description language (HDL).[5] The later mor1kx implementation, which has some advantages compared to the OR 1200,[6] was designed by Julius Baxter and is also written in Verilog. Software simulators also exist[7] which implement the OR1k specification.
The hardware design was released under theGNU Lesser General Public License (LGPL), while the models and firmware were released under theGNU General Public License (GPL).
A referencesystem on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named theOpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running onfield-programmable gate arrays (FPGAs),[8][9] and there have been several commercial derivatives produced.
Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.[10]
The instruction set is a reasonably simple traditional RISC architecture reminiscent ofMIPS using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.
Another notable feature is a rich set ofsingle instruction, multiple data (SIMD) instructions intended fordigital signal processing.
Most implementations are onfield-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began acrowdfunding project to build a cost-efficientapplication-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community.[citation needed] The project did not reach the goal.
As of May 2024[update], no open-source ASIC had been produced.
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITEFPGA prototyping board, which can run both the OpenRISC 1000 and BA12.Flextronics (Flex) andJennic Limited manufactured the OpenRISC as part of anapplication-specific integrated circuit (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).[11] Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.[12]
Cadence Design Systems have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed toAccellera).[13]
TechEdSat, the firstNASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.[14][15][16]
Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz[17] and his team at the Institute for Integrated Systems at theTechnische Universität München have used OpenRISC in research intomulti-core processor architectures.[18]TheOpen Source Hardware User Group (OSHUG) in the UK has on two occasions[19][20] run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,[21] which attracted the interest ofElectronic Engineering Times (EE Times).[22]Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator inJavaScript, runningLinux withX Window System andWayland support.[23]
The OpenRISC community have ported theGNU toolchain to OpenRISC to support development in theprogramming languagesC andC++. Using this toolchain thenewlib,uClibc,musl (as of release 1.1.4), andglibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphicalintegrated development environment (IDE) based on this toolchain. A project to portLLVM to the OpenRISC 1000 architecture began in early 2012.[24]
GCC 9 released with OpenRISC support.[25]
The OR1K project provides aninstruction set simulator, or1ksim. The flagship implementation, the OR1200, is aregister-transfer level (RTL) model in Verilog HDL, from which aSystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (seeOVPsim), set up by Imperas.
The mainlineLinux kernel gained support for OpenRISC in version 3.1.[26]The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).[27] Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.
Severalreal-time operating systems (RTOS) have been ported to OpenRISC, includingNuttX,RTEMS,FreeRTOS, andeCos.
Since version 1.2,QEMU supports emulating OpenRISC platforms.[28]
