 PMOS SC/MP (ISP-8A/500) | |
| General information | |
|---|---|
| Launched | April 1976; 49 years ago (April 1976) |
| Common manufacturer | |
| Performance | |
| Max.CPUclock rate | 1 MHz to 4 MHz |
| Data width | 8 bits |
| Address width | 16 bits |
| Physical specifications | |
| Package |
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| History | |
| Successors | SC/MP-2 INS 8060 SC/MP-3 INS 807x |
National Semiconductor'sSC/MP (pronouncedscamp) forSimple Cost-effective Micro Processor, is an early8-bitmicroprocessor which became available in April 1976. It was designed to allow systems to be implemented with the minimum number of additional supportchips. SC/MP included a daisy-chained control pin that allowed up to three SC/MP's share a single main memory to produce amultiprocessor system, or to act as controllers in a system with another maincentral processing unit (CPU). Three versions were released over its lifetime, SCMP-1 through 3, the latter two also known asINS8060 andINS8070.
To lower cost, the system used abit-serialarithmetic logic unit (ALU) and was thus significantly slower than contemporary designs like theIntel 8080 orMOS 6502 which had parallel ALUs. Another oddity was that theprogram counter could only access the lower 12-bits of the16-bit address, and the upper 4-bits had to be set using special instructions. The result was that instructions accessedmain memory as sixteen 4 KB "pages" and reaching memory outside those pages required multiple instructions.[a]
The combination of slow speed and paged memory limited its attractiveness outside the embedded markets it was aimed at, and in this market it competed against theFairchild F8 which had a number of useful additional features and cost less than a dollar more at 100-unit quantities. The system saw relatively little use.Signetics licensed the design as asecond source but it is unclear whether they produced any.
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Thearithmetic logic unit (ALU) wasaccumulator-based, with a single 8-bit accumulator, AC. A second 8-bit register, "Extension", or E, can be used as a backup for AC. E cannot be accessed directly by most instructions; one cannot load data from memory directly into E. Instead, the value in AC can be read from E, or AC and E can be swapped. E can also be used as the source value for the seven logical/arithmetic operations supported by the ALU, so one canADD to AC using memory, an immediate, or E. If E is not being used for other operations, it can also be used in a fashion similar to the mirror registers seen in designs like theZilog Z80, with E acting as a quicker way to store the value of AC during aninterrupt.[1]
A major purpose of E is to act as a buffer for the built-inserial I/O system.[2] This is driven by the SIO instruction, whichbit shifts the least significant bit in E to alatch which is connected to the SOUT pin on the processor. Repeated calls to SIO presents bits of the 8-bit E value one at a time to the output or reverses this operation for reading from the SIN pin.[3] Once a complete 8-bit value had been read or written, the value can be sent to memory by exchanging the value with AC and then loading or storing AC to memory.[1] E can also be used as the source for logical operations on AC, so one can read a status byte in from the serial port and thenAND that value with a mask in AC, to check for various status bits read from an external device.[4]
The E register can also be substituted as the offset for PC-relative, indexed, and auto-indexed memory reference instructions. When the second byte of these instructions equals -128 (0x80), E is added to the specified P register.[5]
The separate Status Register is 8-bits. The three least-significant-bits, 0 through 2, are connected directly to output pins, providing an easy way to output single bits.[1] A further two pins, Sense A and Sense B, are connected to bits 4 and 5. Sense A was normally used to service interrupts (see details below). Interrupts can be turned off by setting bit 3, Interrupt Enable (IE) to 0 with the Disable Interrupt instruction,DINT, and enabled withIEN, or by moving the value to and from AC and manipulating it there. Sense B is an additional single bit input. Bits 6 and 7 are conventional overflow and carry flags.[6] Although there is no explicit zero flag, zero is determined from the current content of AC.
Like most 8-bit microprocessors of the era, the SC/MP is based around a16-bit address bus and an8-bitdata bus. To reduce pin count, the external address bus contains only 12 pins, multiplexing 4 pins on the data bus to create a complete 16-bit address.[2] The processor only directly modifies the lower 12-bits of theprogram counter. There are separate instructions to set the upper four bits by copying an 8-bit value into the high byte. This provides a memory map of sixteen four-kilobyte pages. Program code cannot refer to code or PC-relative data outside its own page.[5] This leads to a curiosity of the design: when the program counter reaches the end of a page, it does not move to the next page, it returns to the start of the current page.[2]
Addressing was further limited by the two-byte instruction format, which used one byte for theopcode and a second one to indicate an offset between -128 and +127, which was added to a value in aregister to produce a 12-bit address. For instance, an address might refer to a location in memory by saying it is +10 locations from the value in theprogram counter, or +10 from the value in one of the 16-bitindex registers. To access a location outside that range, the page has to be explicitly stored in one of the index registers.[5] Because the registers are 16-bit, and the accumulator that loads values is 8-bit, setting a complete address requires several instructions.[7]
As indexes were critical to the addressing model, the SC/MP included four index registers, the "Pointer Registers" P0 through P3. P0 was the program counter, and not normally manipulated by user programs. By convention, P1 was normally used as a pointer into ROM, P2 into RAM, and P3 was used to store an address duringinterrupts andsubroutine calls.[6] The SC/MP did not have astack, where return values were normally stored on most contemporary designs. Programs had to save return addresses with explicit code.[7]
There were four primary addressing modes, PC-relative, indexed, immediate (meaning a constant in the instruction's second byte as opposed to an offset), and auto-indexed. PC-relative addressing was actually the same as indexed, selecting P0 as the index register.[5]
Auto-indexing aids in the construction of loops. If the displacement is less than zero, the contents of the Pointer Register is decreased by the displacement before the contents of the effective address are fetched or stored. If the displacement is equal to or greater than zero, the contents of the Pointer Register are used as the effective address, and the contents of the Pointer Register are increased by the displacement after the contents of the effective address are fetched or stored. This removes the need for a separate instruction to change the value in the register, so one could store the starting value of a block of data in memory in a pointer register and then loop through all of the data by calling a single instruction.[5] If the offset is negative,@-1(P2), it performs the decrement before accessing the final value. If it is positive.@1(P2), it does a post-increment.[7] This predecrement-postincrement behavior makes it possible to create aLIFO stack. Top of stack is accessed with(P2).
The system includes automatic handling of interrupts on the Sense A line. When an interrupt is received and IE is high (enabled), before starting to fetch the next instruction the system instead clears IE to prevent another interrupt, and then exchanges the values in PC and P3 usingXPPC. This has the effect of saving the return address in P3 and sending the next instruction into the interrupt handler entry point previously stored in P3.[8]
The system does not include the equivalent of a return-from-interrupt. This can be performed with anotherXPPC, copying the previously-saved address in P3 back to the PC and execution continues where it left off. However, this leaves the wrong address in P3, not the start of the interrupt handler, but the end. To address this, the common solution is to place theXPPC that returns to the main code one instruction above the handler entry point, rather than at the end. When the handler completes, it jumps back to this instruction, so whenXPPC is executed, the PC is pointed one location before the proper entry point. Because the system increments the PC before calling an instruction, this means the next interrupt will result it in entering at the correct entry point. This "exit handler" normally also sets the IE to 1 to re-enable interrupts.[9]
Interrupt latency is not quick. When an interrupt is encountered, the SC/MP requires 17 instructions generating 26 bytes of object code to save its status. The olderIntel 8080 requires just four instructions generating four bytes.[10]
A feature of the SC/MP was a shared daisy-chained control line that allowed multiple SC/MP, or more commonly a single SC/MP and relateddirect memory access (DMA) controllers, to share access to a singlemain memory. When any one of the chips on the bus desired access to memory, it would set the ENOUT pin high, thereby signalling the other chip's ENIN pins that they had to release the bus. With most other processors, this would normally require external logic implemented by the board designers to pause the CPU to the same end, often with some complexity due to the internal instruction timing that was not visible to the external circuits. In the SC/MP this was all included internally so a single line on the circuit board was all that was needed to implement this feature.[11]
The original idea was to ease the creation ofmicrocontroller-like applications containing an SC/MP, one or more DMA controllers, and a single shared memory. Designed specifically to be as low-cost as possible in terms of an overall system, the desire to lower the cost of the SC/MP itself also led to decisions about the bit-serial ALU and the inclusion of serial input/output lines to eliminate the need for a separateUART (this feature was removed in the later SC/MP III).[12] Osborne's review of the system stated it was the "microprocessor of choice in any multi-processor application"[13] but this market seems to have been limited as sales were never particularly strong.
The SC/MP does not include a jump-to-subroutine instruction. Instead, theassembler language includes aJSmacro that writes a series of instructions to implement this functionality. The macro loads the high byte of the address into AC, and then executsXPAH to move it to the high byte of a selected pointer register. It then repeats this for the low byte usingXPAL. It then executsXPPC to transfer the resulting 16-bit value from the pointer register to the PC. This sequence generates five bytes and overwrites AC. SinceXPPC exchanges the two values, the current value of the PC is thus stored into the selected pointer register, and the return-from-subroutine can be implemented with a single XPPC to copy the value back. Nested subroutines are not supported though they can be implemented with additional code.[14]
SC/MP increments the program counterbefore fetching the instruction, so that on reset it actually starts executing instructions from location 0001, not 0000. This also needs to be taken into account for calculating displacements, since the offset will be added to the program counter which will be still pointing to the location of the displacement and not the next instruction.
The system included a Delay instruction,DLY, which took a single parameter, P. This stopped operation for a period of 13 + (2 x P) + (2^9 x P) + (2 x AC) microcycles, which it did by continually decrementing the value in AC until it reached zero.[15] This meant it could produce a delay between 13 and 131,593 cycles.[13] This was normally used with the serial pins; a program could set the value in AC to the time it took to transmit a single bit at a given speed and then check the value of one of the flag pins to see if it was ready for the next one.[15] Osborne notes that this feature is of limited practical use, the processor is "spinning" during the delay and this could be accomplished by writing a loop.[13]
The processor was not particularly picky about timing, and in low-speed applications it did not need to use acrystal oscillator and this could be replaced with a simplecapacitor instead.[16]
The SC/MP included an internal clock oscillator. This was common in nMOS designs like the 6502, but unusual for a chip originally fabricated inP Channel MOS (pMOS). Most pMOS processors required a separate external oscillator and clock driver, so this was an advantage for this design as it eliminated the need for one external chip. This did, however, limit the speed to 1 MHz. The SC/MP-2 usedN Channel MOS (nMOS) fabrication but was otherwise identical, which allowed it to run at up to 4 MHz.[2]
There were three major versions:
Montgomery Elevator Co of Moline IL (later purchased byKONE, Inc) used the SC/MP as the basis for its first micro processor based elevator controller released in 1975. There are still many of these units running in buildings across the USA.
The SC/MP was used as the basis of a single board microcontroller produced by Science of Cambridge (laterSinclair Research Ltd) called theMK14. This was based on National's own Introkit design, and National offered Sinclair a deal on completed sets which could not be matched by building their own. This allowed the MK14 to sell for the extremely low cost of £39.95.
Doug Neubauer, best known as the author ofStar Raiders, had moved toAtari after working at National on a product identified only as a "home computer product".[17] This had progressed to the stage of awire wrapped prototype before the company killed it.[18]
The followingassembler source code is for a subroutine CPYMEM that copies bytes from one location to another. This routine uses an unusual @1(P1) addressing mode that is used to index through the memory. This routine can be used to copy between pages but cannot cross a page. This subroutine can be executed from ROM or RAM. If executing from RAM, loop counting could be accelerated with aDLD instruction using a PC-relative counter.
10001000 031001 011002 C5 011004 CE 011006 C4 FE1008 701009 9C F6100B 3F | ; Copy memory words addressed by P1 to location addressed; by P2 for a length of up to 255 bytes. Length is passed; in AC (accumulator). Return address in P3.=X'1000CPYMEM:SCL; Set carry for upcoming ADDCPYLP:XAE; Save count in ELD@1(P1); Get byte to copy, inc P1ST@1(P2); Save save it, inc P2LDI-2; -2 to AC to decrementADE; E (set carry made it -1)JNZCPYLP;Continue for all bytesXPPCP3;Return to caller |