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Incomputer science, aNOP,no-op, orNOOP (pronounced "no op"; short forno operation) is amachine language instruction and itsassembly language mnemonic,programming language statement, orcomputer protocol command that does nothing.
Some computerinstruction sets include an instruction whose purpose is to not change the state of any of the programmer-accessibleregisters,status flags, ormemory. It often takes a well-defined number ofclock cycles to execute. In other instruction sets, there is no explicit NOP instruction, but the assembly language mnemonic NOP represents an instruction which acts as a NOP; e.g., on theSPARC,sethi 0, %g0.
A NOP must not access memory, as that could cause amemory fault orpage fault.
A NOP is most commonly used for timing purposes, to forcememory alignment, to preventhazards, to occupy abranch delay slot, to render void an existing instruction such as a jump, as a target of anexecute instruction, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be problematic or time-consuming). In some cases, a NOP can have minor side effects; for example, on theMotorola 68000 series of processors, the NOP opcode causes a synchronization of thepipeline.[1]
Listed below are the NOP instruction for some CPU architectures:
| CPU architecture | Instructionmnemonic | Bytes | Opcode | Notes |
|---|---|---|---|---|
| Intelx86CPU family | NOP | 1 | 0x90[2] | 0x90 is the one-byte encoding forXCHG AX,AX in 16-bit code andXCHG EAX,EAX in 32-bit code. In long mode,XCHG RAX,RAX requires two bytes, as it would begin with anREX.W prefix, making the encoding 0x48 0x90. However, 0x90 is interpreted as aNOP in long mode regardless of whether it is preceded by 0x48.[2] |
multi-byteNOP | 2–9 forPentium Pro and later Intel processors, and all AMD AMD64 processors | 0x66 0x90 0x0F 0x1F 0x00 0x0F 0x1F 0x40 0x00 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00[2] | 0x66 is the operand-size override prefix. 0x0F 0x1F is a two-byte NOP opcode that takes aModR/M operand upon which no memory is accessed and no registers are written. ModR/M and operands added to this are: 0x00 is 0x40 0x00 is 0x44 0x00 0x00 is 0x80 0x00 0x00 0x00 0x00 is 0x84 0x00 0x00 0x00 0x00 0x00 is | |
FNOP | 2 | 0xD9 0xD0 | x87 floating-point coprocessor no-operation | |
| Intel 8008 | LAA | 1 | 0xC0 | Load A from A |
| Intel 8048 / MCS-48 family | NOP | 1 | 0x00 | |
| Intel8051 /MCS-51 family | NOP | 1 | 0x00 | |
| Intel 8080,8085,Zilog Z80 | NOP | 1 | 0x00 | |
| Intel i860 | NOP | 4 | 0xA0000000 | Core no-operation. Opcode forshl r0,r0,r0, an instruction to left-shift the all-0s register by itself.[3] |
FNOP | 4 | 0xB0000000 | Floating-point no-operation. Opcode forshrd r0,r0,r0, a shift-right-double instruction that takes the all-0s register as input and output.[3] | |
| Intel i960 | MOV g0,g0 | 4 | 0x5C801610 | Move global register g0 to itself. Suggested opcode for cases where a no-op is needed.[4] |
| IntelIA-64 (Itanium) | (qp) NOP.b imm21 | 41 bits | 0x04000000000 | On IA-64, theNOP instruction has five forms, each of which can be executed only on a particular execution unit type.[5]All five The |
(qp) NOP.f imm21 | 41 bits | 0x00008000000 | ||
(qp) NOP.i imm21 | ||||
(qp) NOP.m imm21 | ||||
(qp) NOP.x imm62 | 41+41 bits | 0x00008000000 imm41 | ||
| 32-bit ARM (A32) | NOP | 4 | 0x*320F000 | Architectural ARM A32 NOP ("true" nop, with no register dependencies). Introduced with ARMv6K (ARM 1176, released in 2003), and present in all later ARM A32 processors. (The * indicates a 4-bit field that may take any value other than 0xF.)[6] |
MOV r0,r0/NOP | 4 | 0xE1A00000 | Recommended A32 no-operation encoding for older 32-bit ARM processors that pre-date ARMv6K. Assemblers for A32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6K or later versions of the ARM architecture.[7][8] | |
ANDEQ r0,r0,r0 | 4 | 0x00000000 | Bitwise-AND r0 with itself if equal. Commonly used no-op encoding due to the simplicity of its encoding.[9] | |
MOVNV r0,r0 | 4 | 0xF1A00000 | Move r0 to itself never. Obsolete no-op encoding that used to be recommended for the ARM2/ARM3 processors in olderAcorn Archimedes computers.[9][10] Makes use of the NV ("never") condition code – which has been deprecated since 1993,[11] with support fully removed with ARMv5.[12] | |
| Thumb | MOV r8,r8/NOP | 2 | 0x46C0 | Recommended Thumb no-operation encoding for older 32-bit Thumb processors that pre-date ARMv6T2. Assemblers for T32 will usually output this opcode when given the "NOP" mnemonic unless they are told to target ARMv6T2 or later versions of the ARM Thumb architecture.[7][8] |
| Thumb-2 (T32) | NOP | 2 | 0xBF00 | Architectural ARM T32 (Thumb-2) NOPs ("true" nops, with no register dependencies). Introduced with ARMv6T2 (ARM 1156, released in 2003), and present in all later ARM T32 processors.[6] |
NOP.W | 4 | 0xF3AF8000 | ||
| 64-bit ARM (A64) | NOP | 4 | 0xD503201F | Architectural NOP |
| DEC Alpha | NOP | 4 | 0x47FF041F | Integer NOP. Opcode forBIS r31,r31,r31, an instruction that bitwise-ORs the always-0 register with itself.[13] |
FNOP | 4 | 0x5FFF041F | Floating-point NOP. Opcode forCPYS f31,f31,f31, an instruction that performs copy-sign with the always-0 register as source for both sign and exponent/mantissa, and stores the result in the always-0 register.[13] | |
UNOP | 4 | 0x2FFE0000 | Universal NOP. Opcode forLDQ_U r31,0($sp). The LDQ_U (unaligned load) opcode is, on 21164 and later, special-cased so that when used with the always-0 register as a destination register, no memory access is performed.[13][14] The address register and displacement may take any value, but is most commonly given as0($sp) which isstack pointer + zero.[15] | |
| AMD 29k | NOP | 4 | 0x70400101 | Opcode foraseq 0x40,gr1,gr1, an instruction that asserts that thestack register is equal to itself.[16] |
| AVR | NOP | 2 | 0x0000 | one clock cycle |
| COP400 | NOP | 1 | 0x44 | |
| COP8 | NOP | 1 | 0xB8 | |
| HP 3000 | NOP | 2 | 0x0000 | HP 3000 stack operation instructions have most-significant four bits of 0 followed by two 6-bit stack opcodes, with stack NOP (0) used to pad when needed. 0x0000 would be NOP, NOP.[17] |
| Hyperstone E1 | NOP | 2 | 0x0300 | Opcode forCHK L0,L0, a range-check instruction which produces an exception if the L0 register is greater than itself.[18] |
| IBM System/360,IBM System/370,IBM System/390,z/Architecture,UNIVAC Series 90 | NOP | 4 | 0x47000000 or 0x470nnnnn or 0x47n0nnnn where "n" is any 4-bit value. | The NOP ("No-Op") and NOPR ("No-Op Register") are a subset of the "Branch on Condition" or "Branch on Condition Register" instructions, respectively; both versions have two options for generating a NO-OP. In the case of both the NOP and NOPR instructions, the first 0 in the second byte is the "mask" value, the condition to test such as equal, not equal, high, low, etc. If the mask is 0, no branch occurs. In the case of the NOPR instruction, the second value in the second byte is the register to branch on. If register 0 is chosen, no branch occurs regardless of the mask value. Thus, if either of the two values in the second byte is 0, the branch will not happen. If the first 0 in the second byte is 0, the value of the second value in the second byte is irrelevant on most processors; however, on theIBM System/360 Model 91, if that value refers to register 15, the instruction will wait for all previously-decoded instructions to complete before continuing.[19] In the case of the NOP instruction, the second value in the second byte is the "base" register of a combined base register, displacement register and offset address. If the base register is also 0, the branch is not taken regardless of the value of the displacement register or displacement address. |
NOPR | 2 | 0x0700 or 0x070n or 0x07n0 where "n" is any 4-bit value. | ||
| LoongArch | NOP | 4 | 0x03400000 | Opcode forandi r0,r0,0, an instruction that bitwise-ANDs the always-0 register with zero.[20] |
| MicroBlaze | NOP | 4 | 0x80000000 | Opcode foror r0,r0,r0, an instruction that bitwise-ORs the always-0 register with itself.[21] |
| MIPS | NOP | 4 | 0x00000000 | Stands forsll r0,r0,0, meaning: Logically shift register 0 zero bits to the left and store the result in register 0. Writes to register 0 are ignored; it always contains 0. |
| MIPS-X | NOP | 4 | 0x60000019 | (extended opcode foradd r0,r0,r0) |
| MIX | NOP | 1 word | ± * * * * 0 | The * bytes are arbitrary, and can be anything from 0 to the maximum byte (required to be in the range 63-99). MIX uses sign-magnitude representation. |
| MMIX | SWYM | 4 | 0xFD****** | SWYM stands for "Sympathize with your machinery". The * digits can be chosen arbitrarily. |
| MOS Technology 65xx (e.g.6502), WDC 65C816 | NOP | 1 | 0xEA | NOP consumes two clock cycles.Undefined opcodes in theNMOS versions of the 65xx family were converted to be NOPs of varying instruction lengths and cycle times in the65C02. |
| Motorola 6800 | NOP | 1 | 0x01 | |
| Motorola 68000 family | NOP | 2 | 0x4E71 | This synchronizes thepipeline and prevents instruction overlap.[1]: 3-21 [1]: 4-147 |
TRAPF,TRAPF.W #data,TRAPF.L #data | 2, 4, 6 | 0x51FC, 0x51FA 0xnnnn, 0x51FB 0xnnnn 0xnnnn | Trap if false. Suggested opcode for68020 and later 68k processors if a NOP without pipeline synchronization is desired. ('n' may take any 4-bit value.)[1]: 3-21 [1]: 4-189 | |
| Motorola 6809 | NOP | 1 | 0x12 | |
| Motorola 88000 family | BCND lt0,r0,X,ADD r0,r0,r0,TB1 0,r0,x | 4 | 0xE980xxxx, 0xF4007000, 0xF000D8xx | Branch if always-0 register is less than 0, Add always-0 register to itself, Trap if bit 0 of always-0 register is 1 (serializing).[22] |
| MSP430 | NOP | 2 | 0x4303 | Opcode formov #0,r3 ormov r3,r3, an instruction that performs a move from a "constant generation register" to itself.[23] |
| PA-RISC | NOP | 4 | 0x08000240 | Opcode forOR 0,0,0.[24] |
LDI 26,0 | 4 | 0x34000034 | Palindromic NOP – that is, an instruction that executes as NOP regardless of whether byte order is interpreted aslittle-endian or big-endian. Some PA-RISC system instructions are required to be followed by seven palindromic NOPs.[24] | |
| PDP-6,PDP-10 | JFCL 0, (conventional)JUMP, SETA, SETAI, CAI, TRN, TLN | 1 word | 25500******* (octal) | Jump never Jump never, set nothing, skip never |
| PDP-11 | NOP | 2 | 000240 (octal) | Clear none of the condition codes |
| PIC microcontroller | NOP | 12 bits | 0b000000000000 | Number of bits in NOP varies by series. |
| POWER,PowerPC,Power ISA | NOP | 4 | 0x60000000 | Opcode forori r0,r0,0.Under the Power ISA, many apparent no-op instruction encodings have significant side-effects – therefore, no-op encodings other than
|
| RISC-V | NOP | 4 | 0x00000013 | ADDI x0, x0, 0 |
C.NOP | 2 | 0x0001 | C.ADDI x0, 0. Only available on RISC-V CPUs that support the "C" (compressed instructions) extension.[29] | |
| Signetics 8X300 | MOV AUX, AUX | 2(16 bits) | 0x0000 | Move AUX to AUX with no rotate |
| SPARC | NOP | 4 | 0x01000000 | Stands forsethi 0, %g0 which zeroes the hardwired-to-zero%g0 register[30] |
| Sunplus S+core | NOP | 4 | 0x80008000 | Architectural NOPs[31] |
NOP! | 2 | 0x0000 | ||
| SuperH | NOP | 2 | 0x0009 | [32] |
NOP | 4 | 0x6FF0FFF0 | 32-bit NOP, present on SH-5 only.[33] | |
| Tensilica Xtensa | NOP,_NOP | 3 | 0x0020F0 | Assemblers may convert "NOP" to "NOP.N" – the "_NOP" mnemonic (with a leading underscore) can be used to prevent such conversion.[34] |
NOP.N | 2 | 0xF03D | ||
| VAX | NOP | 1 | 0x01 | Delay is dependent on processor type. |
| WD16 | NOP | 2 | 0x0000 | |
From a hardware design point of view, unmapped areas of a bus are often designed to return zeroes; since theNOP slide behavior is often desirable, it gives a bias to coding it with the all-zeroes opcode.
A function or a sequence of programming language statements is a NOP or null statement if it has no effect. Null statements may be required by thesyntax of some languages in certain contexts.
InAda, thenull statement serves as a NOP.[35] As the syntax forbids that control statements or functions be empty, thenull statement must be used to specify that no action is required. (Thus, if the programmer forgets to write a sequence of statements, the program will fail to compile.)
The simplest NOP statement in C is thenull statement, which is just a semi-colon in a context requiring a statement.
Most C compilers generate no code for null statements, which has historical and performance reasons.
;
An empty block (compound statement) is also a NOP, and may be more legible, but will still have no code generated for it by the compiler.
{}In some cases, such as the body of a function, a block must be used, but this can be empty. In C, statements cannot be empty—simple statements must end with a; (semicolon) while compound statements are enclosed in{} (braces), which does not itself need a following semicolon. Thus in contexts where a statement is grammatically required, some such null statement can be used.
The null statement is useless by itself, but it can have a syntactic use in a wider context, e.g., within the context of a loop:
while(getchar()!='\n'){}
alternatively,
while(getchar()!='\n');
or more tersely:
while(getchar()!='\n');
The last form might generate a warning with some compilers or compiler options, as a semicolon placed after a parenthesis at the end of a line usually indicates the end of a function call expression.
The above code continues calling the functiongetchar() until it returns a\n (newline) character, essentially fast-forwarding the current reading location of standard input to the beginning of next line.
InFortran, theCONTINUE statement is used in some contexts such as the last statement in a DO loop, although it can be used anywhere, and does not have any functionality.
TheJavaScript language does not have a built-in NOP statement. Many implementations are possible:
;empty statement[36] or the{} emptyblock statement the same way as in theC and derivatives examples;undefined or thenull expression as a complete statement (anexpression statement) when the previous methods are not allowed by the syntax.Alternatives, in situations where a function is required, are:
Function.prototype() built-in function, that accepts any arguments and returnsundefined;[37]constnoop=()=>{};
TheAngularJS framework providesangular.noop function that performs no operations.
ThejQuery library provides a functionjQuery.noop(), which does nothing.[38]
TheLodash library provides a function_.noop(), which returns undefined and does nothing.[39]
As with C, the ; used by itself can be used as a null statement inPascal. In fact, due to the specification of the language, in a BEGIN / END block, the semicolon is optional before the END statement, thus a semicolon used there is superfluous.
Also, a block consisting of BEGIN END; may be used as a placeholder to indicate no action, even if placed inside another BEGIN / END block.
ThePython programming language has apass statement which has no effect when executed and thus serves as a NOP. It is primarily used to ensure correct syntax due to Python'sindentation-sensitive syntax; for example the syntax for definition of aclass requires an indented block with the class logic, which has to be expressed aspass when it should be empty.
The ':' [colon] command is a shell builtin that has similar effect to a "NOP" (a do-nothing operation). It is not technically an NOP, as it changes the special parameter $? (exit status of last command) to 0. It may be considered a synonym for the shell builtin 'true', and its exit status is true (0).[40][41][42]
TheTeX typographical system's macro language has the\relax command.[43] It does nothing by itself, but may be used to prevent the immediately preceding command from parsing any subsequent tokens.[44]
Manycomputer protocols, such astelnet, include a NOP command that a client can issue to request a response from the server without requesting any other actions. Such a command can be used toensure the connection is still alive or that the server is responsive. A NOOP command is part of the following protocols (this is a partial list):
Unlike the other protocols listed, the IMAP4 NOOP command has a specific purpose—it allows the server to send any pending notifications to the client.
While mosttelnet orFTP servers respond to a NOOP command with "OK" or "+OK", some programmers have added quirky responses to the client. For example, theftpd daemon ofMINIX responds to NOOP with the message:[45]
200 NOOP to you too!
NOPs are often involved whencracking software that checks for serial numbers, specific hardware or software requirements, presence or absence of hardwaredongles, etc. in the form of aNOP slide. This process is accomplished by alteringfunctions and subroutines to bypass security checks and instead simply return the expected value being checked for. Because most of the instructions in the security check routine will be unused, these would be replaced with NOPs, thus removing the software's security functionality without altering the positioning of everything which follows in the binary.
The NOP opcode can be used to form aNOP slide, which allows code to execute when the exact value of the instruction pointer is indeterminate (e.g., when a buffer overflow causes a function's return address on the stack to be overwritten).
NOPL, the official longNOPNote that NOP is a special case of the SETHI instruction, with imm22 = 0 and rd = 0.
The execution of a null_statement has no effect.
The empty statement is a semicolon (;) indicating that no statement will be executed, even if JavaScript syntax requires one.According to The TeXbook, 'TeX does nothing' when it encounters\relax. Actually,\relaxmay tell TeX, 'This is the end of what you've been doing'.