| Program execution |
|---|
| General concepts |
| Types of code |
| Compilation strategies |
| Notable runtimes |
|
| Notable compilers & toolchains |
|
Inprocessor design,microcode serves as an intermediary layer situated between thecentral processing unit (CPU) hardware and the programmer-visibleinstruction set architecture of a computer.[1] It consists of a set of hardware-level instructions that implement the higher-levelmachine code instructions or control internalfinite-state machine sequencing in manydigital processing components. While microcode is utilized inIntel andAMD general-purpose CPUs in contemporary desktops and laptops, it functions only as a fallback path for scenarios that the fasterhardwired control unit is unable to manage.[2]
Housed in special high-speed memory, microcode translates machine instructions,state machine data, or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlyingelectronics, thereby enabling greater flexibility in designing and altering instructions. Moreover, it facilitates the construction of complex multi-step instructions, while simultaneously reducing the complexity of computer circuits. The act of writing microcode is often referred to asmicroprogramming, and the microcode in a specific processor implementation is sometimes termed amicroprogram.
Through extensive microprogramming,microarchitectures of smaller scale and simplicity canemulate more robust architectures with widerword lengths, additionalexecution units, and so forth. This approach provides a relatively straightforward method of ensuring software compatibility between different products within a processor family.
At the hardware level, processors contain a number of separate areas of circuitry, or "units", that perform different tasks. Commonly found units include thearithmetic logic unit (ALU) which performs instructions such as addition or comparing two numbers, circuits for reading and writing data to external memory, and small areas of onboard memory to store these values while they are being processed. In most designs, additional high-performance memory, theregister file, is used to store temporary values, not just those needed by the current instruction.[3]
To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. InRISC designs, the proper ordering of these instructions is largely up to the programmer, or at least to thecompiler of theprogramming language they are using. So to add two numbers in memory and store the result in memory, for instance, the compiler may output instructions to load one of the values into one register, the second into another, perform the addition function in the ALU, putting the result into a register, and then store that register into memory.[3]
As the sequence of instructions needed to complete this higher-level concept, "add these two numbers in memory", may require multiple instructions, this can represent a performance bottleneck if those instructions are stored inmain memory. Reading those instructions one by one takes time that could be used to read and write the actual data. For this reason, it is common for non-RISC designs to have many different instructions that differ largely on where they store data. For instance, theMOS 6502 has eight variations of the addition instruction,ADC, which differ only in where they look to find the two operands.[4]
Using the variation of the instruction, or "opcode", that most closely matches the ultimate operation can reduce the number of instructions to one, saving memory used by the program code and improving performance by leaving thedata bus open for other operations. Internally, however, these instructions are not separate operations, but sequences of the operations the units actually perform. Converting a single instruction read from memory into the sequence of internal actions is the duty of thecontrol unit, another unit within the processor.[5]
The basic idea behind microcode is to replace the custom hardware logic implementing the instruction sequencing with a series of simple instructions run in a "microcode engine" in the processor. Whereas a custom logic system might have a series of diodes and gates that output a series of voltages on various control lines, the microcode engine is connected to these lines instead, and these are turned on and off as the engine reads the microcode instructions in sequence. The microcode instructions are often bit encoded to those lines, for instance, if bit 8 is true, that might mean that the ALU should be paused awaiting data. In this respect microcode is somewhat similar to the paper rolls in aplayer piano, where the holes represent which key should be pressed.
The distinction between custom logic and microcode may seem small, one uses a pattern of diodes and gates to decode the instruction and produce a sequence of signals, whereas the other encodes the signals as microinstructions that are read in sequence to produce the same results. The critical difference is that in a custom logic design, changes to the individual steps require the hardware to be redesigned. Using microcode, all that changes is the code stored in the memory containing the microcode. This makes it much easier to fix problems in a microcode system. It also means that there is no effective limit to the complexity of the instructions, it is only limited by the amount of memory one is willing to use.
The lowest layer in a computer's software stack is traditionally rawmachine code instructions for the processor. In microcoded processors, fetching and decoding those instructions, and executing them, may be done by microcode. To avoid confusion, each microprogram-related element is differentiated by themicro prefix: microinstruction, microassembler, microprogrammer, etc.[6]
Complex digital processors may also employ more than one (possibly microcode-based)control unit in order to delegate sub-tasks that must be performed essentially asynchronously in parallel. For example, theVAX 9000 has a hardwired IBox unit to fetch and decode instructions, which it hands to a microcoded EBox unit to be executed,[7] and theVAX 8800 has both a microcoded IBox and a microcoded EBox.[8]
A high-level programmer, or even anassembly language programmer, does not normally see or change microcode. Unlike machine code, which often retains somebackward compatibility among different processors in a family, microcode only runs on the exactelectronic circuitry for which it is designed, as it constitutes an inherent part of the particular processor design itself.
Engineers normally write the microcode during the design phase of a processor, storing it in aread-only memory (ROM) orprogrammable logic array (PLA)[9] structure, or in a combination of both.[10] However, machines also exist that have some or all microcode stored instatic random-access memory (SRAM) orflash memory. This is traditionally denoted aswritablecontrol store in the context of computers, which can be either read-only orread–write memory. In the latter case, the CPU initialization process loads microcode into the control store from another storage medium, with the possibility of altering the microcode to correct bugs in the instruction set, or to implement new machine instructions.
Microprograms consist of series of microinstructions, which control the CPU at a very fundamental level of hardware circuitry. For example, a single typicalhorizontal microinstruction might specify the following operations simultaneously:
To simultaneously control all processor's features in one cycle, the microinstruction is often wider than 50 bits; e.g., 128 bits on a360/85 with an emulator feature. Microprograms are carefully designed and optimized for the fastest possible execution, as a slow microprogram would result in a slow machine instruction and degraded performance for related application programs that use such instructions.
Microcode was originally developed as a simpler method of developing the control logic for a computer. Initially, CPUinstruction sets werehardwired. Each step needed to fetch, decode, and execute the machine instructions (including any operand address calculations, reads, and writes) was controlled directly bycombinational logic and rather minimalsequential state machine circuitry. While such hard-wired processors were very efficient, the need for powerful instruction sets with multi-step addressing and complex operations (see below) made them difficult to design and debug; highly encoded and varied-length instructions can contribute to this as well, especially when very irregular encodings are used.
Microcode simplified the job by allowing much of the processor's behaviour and programming model to be defined via microprogram routines rather than by dedicated circuitry. Even late in the design process, microcode could easily be changed, whereas hard-wired CPU designs were very cumbersome to change. Thus, this greatly facilitated CPU design.
From the 1940s to the late 1970s, a large portion of programming was done inassembly language; higher-level instructions mean greater programmer productivity, so an important advantage of microcode was the relative ease by which powerful machine instructions can be defined. The ultimate extension of this are "Directly Executable High Level Language" designs, in which each statement of a high-level language such asPL/I is entirely and directly executed by microcode, without compilation. TheIBM Future Systems project andData General Fountainhead Processor are examples of this. During the 1970s, CPU speeds grew more quickly than memory speeds and numerous techniques such asmemory block transfer,memory pre-fetch andmulti-level caches were used to alleviate this. High-level machine instructions, made possible by microcode, helped further, as fewer more complex machine instructions require less memory bandwidth. For example, an operation on a character string can be done as a single machine instruction, thus avoiding multiple instruction fetches.
Architectures with instruction sets implemented by complex microprograms included theIBMSystem/360 andDigital Equipment CorporationVAX. The approach of increasingly complex microcode-implemented instruction sets was later calledcomplex instruction set computer (CISC). An alternate approach, used in manymicroprocessors, is to use one or moreprogrammable logic array (PLA) orread-only memory (ROM) (instead of combinational logic) mainly for instruction decoding, and let a simple state machine (without much, or any, microcode) do most of the sequencing. TheMOS Technology 6502 is an example of a microprocessor using a PLA for instruction decode and sequencing. The PLA is visible in photomicrographs of the chip,[11] and its operation can be seen in thetransistor-level simulation.
Microprogramming is still used in modern CPU designs. In some cases, after the microcode is debugged in simulation, logic functions are substituted for the control store.[citation needed] Logic functions are often faster and less expensive than the equivalent microprogram memory.
A processor's microprograms operate on a more primitive, totally different, and much more hardware-oriented architecture than the assembly instructions visible to normal programmers. In coordination with the hardware, the microcode implements the programmer-visible architecture. The underlying hardware need not have a fixed relationship to the visible architecture. This makes it easier to implement a given instruction set architecture on a wide variety of underlying hardware micro-architectures.
The IBM System/360 has a 32-bit architecture with 16 general-purpose registers, but most of the System/360 implementations use hardware that implements a much simpler underlying microarchitecture; for example, theSystem/360 Model 30 has 8-bit data paths to the arithmetic logic unit (ALU) and main memory and implemented the general-purpose registers in a special unit of higher-speedcore memory, and theSystem/360 Model 40 has 8-bit data paths to the ALU and 16-bit data paths to main memory and also implemented the general-purpose registers in a special unit of higher-speed core memory. TheModel 50 has full 32-bit data paths and implements the general-purpose registers in a special unit of higher-speed core memory.[12] The Model 65 through the Model 195 have larger data paths and implement the general-purpose registers in faster transistor circuits.[citation needed] In this way, microprogramming enabled IBM to design many System/360 models with substantially different hardware and spanning a wide range of cost and performance, while making them all architecturally compatible. This dramatically reduces the number of unique system software programs that must be written for each model.
TheDigital Equipment CorporationPDP-11 is a 16-bitarchitecture with eight general-purpose registers. It was introduced in 1970 and the basic architecture remained unchanged through the 1990s. Only the original machine in the series was not microcoded. From the years 1972 to 1976, the width of the PDP-11's underlying microprogram varied from 22 to 64 bits. The length of the microprogram varied from 256 to 1,024 words with longer microprogram lengths generally corresponding to narrower widths.[13] The variety of microprogram widths imply that there were at least seven different implementations of the PDP-11 in just four years.
A similar approach was used by Digital Equipment Corporation in their VAX family of computers. As a result, different VAX processors use different microarchitectures, yet the programmer-visible architecture does not change.
Microprogramming also reduces the cost of field changes to correct defects (bugs) in the processor; a bug can often be fixed by replacing a portion of the microprogram rather than by changes being made tohardware logic and wiring.
The ACE computer, designed byAlan Turing in 1946, used microprogramming.[14]
In 1947, the design of theMIT Whirlwind introduced the concept of a control store as a way to simplify computer design and move beyondad hoc methods. The control store is adiode matrix: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by theCPU clock and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.[15]
In 1951,Maurice Wilkes[16] enhanced this concept by addingconditional execution, a concept akin to aconditional in computer software. His initial implementation consisted of a pair of matrices: the first one generated signals in the manner of the Whirlwind control store, while the second matrix selected which row of signals (the microprogram instruction word, so to speak) to invoke on the next cycle. Conditionals were implemented by providing a way that a single line in the control store could choose from alternatives in the second matrix. This made the control signals conditional on the detected internal signal. Wilkes coined the termmicroprogramming to describe this feature and distinguish it from a simple control store.
Microcode remained relatively rare in computer design as the cost of the ROM needed to store the code was not significantly different from the cost of custom control logic. This changed through the early 1960s with the introduction of mass-producedcore memory andcore rope, which was far less expensive than dedicated logic based on diode arrays or similar solutions. The first to take real advantage of this wasIBM in their 1964System/360 series. This allowed the machines to have a very complex instruction set, including operations that matched high-level language constructs like formatting binary values as decimal strings, encoding the complex series of internal steps needed for this task in low cost memory.[17]
But the real value in the 360 line was that one could build a series of machines that were completely different internally, yet run the same ISA. For a low-end machine, one might use an 8-bit ALU that requires multiple cycles to complete a single 32-bit addition, while a higher end machine might have a full 32-bit ALU that performs the same addition in a single cycle. These differences could be implemented in control logic, but the cost of implementing a completely different decoder for each machine would be prohibitive. Using microcode meant all that changed was the code in the ROM. For instance, one machine might include afloating point unit and thus its microcode for multiplying two numbers might be only a few lines line, whereas on the same machine without the FPU this would be a program that did the same using multiple additions, and all that changed was the ROM.[17]
The outcome of this design was that customers could use a low-end model of the family to develop their software, knowing that if more performance was ever needed, they could move to a faster version and nothing else would change. This lowered the barrier to entry and the 360 was a runaway success. By the end of the decade, the use of microcode wasde rigueur across the mainframe industry.
Earlyminicomputers were far too simple to require microcode, and were more similar to earlier mainframes in terms of their instruction sets and the way they were decoded. But it was not long before their designers began using more powerfulintegrated circuits that allowed for more complex ISAs. By the mid-1970s, most new minicomputers andsuperminicomputers were using microcode as well, such as most models of thePDP-11 and, most notably, most models of theVAX, which included high-level instruction not unlike those found in the 360.[18]
The same basic evolution occurred withmicroprocessors as well. Early designs were extremely simple, and even the more powerful 8-bit designs of the mid-1970s like theZilog Z80 had instruction sets that were simple enough to be implemented in dedicated logic. By this time, the control logic could be patterned into the same die as the CPU, making the difference in cost between ROM and logic less of an issue. However, it was not long before these companies were also facing the problem of introducing higher-performance designs but still wanting to offerbackward compatibility. Among early examples of microcode in micros was theIntel 8086.[5]
Among the ultimate implementations of microcode in microprocessors is theMotorola 68000. This offered a highlyorthogonal instruction set with a wide variety ofaddressing modes, all implemented in microcode. This did not come without cost, according to early articles, about 20% of the chip's surface area (and thus cost) is the microcode system[19] and[citation needed] of the systems 68,000 transistors were part of the microcode system.
While companies continued to compete on the complexity of their instruction sets, and the use of microcode to implement these was unquestioned, in the mid-1970s an internal project in IBM was raising serious questions about the entire concept. As part of a project to develop a high-performance all-digitaltelephone switch, a team led byJohn Cocke began examining huge volumes of performance data from their customer's 360 (andSystem/370) programs. This led them to notice a curious pattern: when the ISA presented multiple versions of an instruction, thecompiler almost always used the simplest one, instead of the one most directly representing the code. They learned that this was because those instructions were always implemented in hardware, and thus run the fastest. Using the other instruction might offer higher performance on some machines, but there was no way to know what machine they were running on. This defeated the purpose of using microcode in the first place, which was to hide these distinctions.[20]
The team came to a radical conclusion: "Imposing microcode between a computer and its users imposes an expensive overhead in performing the most frequently executed instructions."[20]
The result of this discovery was what is today known as theRISC concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at theUniversity of California, Berkeley, that introduced the term RISC.
The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.[21] A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.[21] Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.[20]
The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for theirDEC Alpha designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, theIntel 80486 uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.[22] ThePentium Pro's fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing soout-of-order. Complex instructions are implemented by microcode that consists of predefined sequences of micro-operations.[23]
Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, usedPALcode to implement features such astranslation lookaside buffer (TLB) miss handling and interrupt handling,[24] as well as providing, for Alpha-based systems runningOpenVMS, instructions requiring interlocked memory access that are similar to instructions provided by theVAX architecture.[24] CMOSIBM System/390 CPUs, starting with the G4 processor, andz/Architecture CPUs usemillicode to implement some instructions.[25]
Each microinstruction in a microprogram provides the bits that control the functional elements that internally compose a CPU. The advantage over a hard-wired CPU is that internal CPU control becomes a specialized form of a computer program. Microcode thus transforms a complex electronic design challenge (the control of a CPU) into a less complex programming challenge. To take advantage of this, a CPU is divided into several parts:
There may also be amemory address register and amemory data register, used to access the maincomputer storage. Together, these elements form an "execution unit". Most modernCPUs have several execution units. Even simple computers usually have one unit to read and write memory, and another to execute user code. These elements could often be brought together as a single chip. This chip comes in a fixed width that would form a "slice" through the execution unit. These are known as "bit slice" chips. TheAMD Am2900 family is one of the best known examples of bit slice elements.[40] The parts of the execution units and the whole execution units are interconnected by a bundle of wires called abus.
Programmers develop microprograms, using basic software tools. Amicroassembler allows a programmer to define the table of bits symbolically. Because of its close relationship to the underlying architecture, "microcode has several properties that make it difficult to generate using a compiler."[1] Asimulator program is intended to execute the bits in the same way as the electronics, and allows much more freedom to debug the microprogram. After the microprogram is finalized, and extensively tested, it is sometimes used as the input to a computer program that constructs logic to produce the same data.[citation needed] This program is similar to those used to optimize aprogrammable logic array. Even without fully optimal logic, heuristically optimized logic can vastly reduce the number of transistors from the number needed for aread-only memory (ROM) control store. This reduces the cost to produce, and the electricity used by, a CPU.
Microcode can be characterized ashorizontal orvertical, referring primarily to whether each microinstruction controls CPU elements with little or no decoding (horizontal microcode)[a] or requires extensive decoding bycombinatorial logic before doing so (vertical microcode). Consequently, each horizontal microinstruction is wider (contains more bits) and occupies more storage space than a vertical microinstruction.
"Horizontal microcode has several discrete micro-operations that are combined in a single microinstruction for simultaneous operation."[1] Horizontal microcode is typically contained in a fairly wide control store; it is not uncommon for each word to be 108 bits or more. On each tick of a sequencer clock a microcode word is read, decoded, and used to control the functional elements that make up the CPU.
In a typical implementation a horizontal microprogram word comprises fairly tightly defined groups of bits. For example, one simple arrangement might be:
| Register source A | Register source B | Destination register | Arithmetic and logic unit operation | Type of jump | Jump address |
For this type of micromachine to implement a JUMP instruction with the address following the opcode, the microcode might require two clock ticks. The engineer designing it would write microassembler source code looking something like this:
# Any line starting with a number-sign is a comment# This is just a label, the ordinary way assemblers symbolically represent a# memory address. InstructionJUMP:# To prepare for the next instruction, the instruction-decode microcode has already# moved the program counter to the memory address register. This instruction fetches# the target address of the jump instruction from the memory word following the# jump opcode, by copying from the memory data register to the memory address register.# This gives the memory system two clock ticks to fetch the next# instruction to the memory data register for use by the instruction decode.# The sequencer instruction "next" means just add 1 to the control word address. MDR, NONE, MAR, COPY, NEXT, NONE# This places the address of the next instruction into the PC.# This gives the memory system a clock tick to finish the fetch started on the# previous microinstruction.# The sequencer instruction is to jump to the start of the instruction decode. MAR,1, PC, ADD, JMP, InstructionDecode# The instruction decode is not shown, because it is usually a mess, very particular# to the exact processor being emulated. Even this example is simplified.# Many CPUs have several ways to calculate the address, rather than just fetching# it from the word following the op-code. Therefore, rather than just one# jump instruction, those CPUs have a family of related jump instructions.
For each tick it is common to find that only some portions of the CPU are used, with the remaining groups of bits in the microinstruction being no-ops. With careful design of hardware and microcode, this property can be exploited to parallelise operations that use different areas of the CPU; for example, in the case above, the ALU is not required during the first tick, so it could potentially be used to complete an earlier arithmetic instruction.
In vertical microcode, each microinstruction is significantly encoded, that is, the bit fields generally pass through intermediate combinatory logic that, in turn, generates the control and sequencing signals for internal CPU elements (ALU, registers, etc.). This is in contrast with horizontal microcode, in which the bit fields either directly produce the control and sequencing signals or are only minimally encoded. Consequently, vertical microcode requires smaller instruction lengths and less storage, but requires more time to decode, resulting in a slower CPU clock.[41]
Some vertical microcode is just the assembly language of a simple conventional computer that is emulating a more complex computer. Some processors, such asDEC Alpha processors and the CMOS microprocessors on later IBM mainframesSystem/390 andz/Architecture, use machine code, running in a special mode that gives it access to special instructions, special registers, and other hardware resources unavailable to regular machine code, to implement some instructions and other functions,[42][43] such as page table walks on Alpha processors.[44] This is calledPALcode on Alpha processors andmillicode on IBM mainframe processors.
Another form of vertical microcode has two fields:
| Field select | Field value |
Thefield select selects which part of the CPU will be controlled by this word of the control store. Thefield value controls that part of the CPU. With this type of microcode, a designer explicitly chooses to make a slower CPU to save money by reducing the unused bits in the control store; however, the reduced complexity may increase the CPU's clock frequency, which lessens the effect of an increased number of cycles per instruction.
As transistors grew cheaper, horizontal microcode came to dominate the design of CPUs using microcode, with vertical microcode being used less often.
When both vertical and horizontal microcode are used, the horizontal microcode may be referred to asnanocode orpicocode.[45]
A few computers were built usingwritable microcode. In this design, rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called awritable control store orWCS. Such a computer is sometimes called awritable instruction set computer (WISC).[46]
Many experimental prototype computers usewritable control stores; there are also commercial machines that use writable microcode, such as theBurroughs Small Systems, earlyXerox workstations, theDECVAX 8800 (Nautilus) family, theSymbolics L- and G-machines, a number of IBM System/360 andSystem/370 implementations, some DECPDP-10 machines,[47] and theData General Eclipse MV/8000.[48]
The IBM System/370 includes a facility calledInitial-Microprogram Load (IML orIMPL)[49] that can be invoked from the console, as part ofpower-on reset (POR) or from another processor in atightly coupledmultiprocessor complex.
Some commercial machines, for example IBM 360/85,[50][51] have both a read-only storage and a writable control store for microcode.
WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs can provide. User-programmable WCS allows the user to optimize the machine for specific purposes.
Starting with thePentium Pro in 1995, severalx86 CPUs have writableIntel Microcode.[52][53] This, for example, has allowed bugs in theIntel Core 2 and IntelXeon microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs –Spectre andMeltdown – which went public at the start of 2018.[54][55] A microcode update can be installed by Linux,[56]FreeBSD,[57] Microsoft Windows,[58] or the motherboard BIOS.[59]
Some machines offer user-programmable writable control stores as an option, including theHP 2100, DECPDP-11/60,TI-990/12,[60][61] andVarian Data Machines V-70 seriesminicomputers. WCS options extended down to microprocessors too. TheDEC LSI-11 has an option to allow programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set.[62]
Some microcode peripheral devices and adapters have writable microcode, which is usually loaded by an operating systemdevice driver. Such microcode is loaded to the device'sSRAM orDRAM, for example,GDDR SDRAM of a video card.
 | This sectiondoes notcite anysources. Please helpimprove this section byadding citations to reliable sources. Unsourced material may be challenged andremoved.(August 2023) (Learn how and when to remove this message) |
 | This section needs to beupdated. The reason given is: Many CISC processors now do instruction fetch and decode in hardware, and execute most if not all instructions in hardware, and both RISC and CISC processors execute several operations per clock cycle. Please help update this article to reflect recent events or newly available information.(December 2023) |
The design trend toward heavily microcoded processors with complex instructions began in the early 1960s and continued until roughly the mid-1980s. At that point theRISC design philosophy started becoming more prominent.
A CPU that uses microcode generally takes several clock cycles to execute a single instruction, one clock cycle for each step in the microprogram for that instruction. SomeCISC processors include instructions that can take a very long time to execute. Such variations interfere with bothinterrupt latency and, what is far more important in modern systems,pipelining.
When designing a new processor, ahardwired control RISC has the following advantages over microcoded CISC:
There are counterpoints as well:
Many RISC andVLIW processors are designed to execute every instruction (as long as it is in the cache) in a single cycle. This is very similar to the way CPUs with microcode execute one microinstruction per cycle. VLIW processors have instructions that behave similarly to very wide horizontal microcode, although typically without such fine-grained control over the hardware as provided by microcode. RISC instructions are sometimes similar to the narrow vertical microcode.
Modern CISC implementations, such as thex86 family starting with theNexGen Nx586, IntelPentium Pro, andAMD K5, decode instructions into dynamically bufferedmicro-operations with an instruction encoding similar to RISC or traditional microcode. A hardwired instruction decode unit directly emits microoperations for common x86 instructions, but falls back to a more traditional microcode ROM containing microoperations for more complex or rarely used instructions.[2]
For example, an x86 might look up microoperations from microcode to handle complex multistep operations such as loop or string instructions,floating-point unittranscendental functions or unusual values such asdenormal numbers, and special-purpose instructions such asCPUID.
ThePDP-8 is a family of12-bitminicomputers that was launchedDigital Equipment Corporation in 1965. TheOPR (OPeRate) instruction was said to be "microcoded." This did not mean what the word means today, but meant that each bit of the instruction word specifies a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. Examples of these actions are: clear accumulator, complement accumulator, rotate right, rotate right twice, and byte swap.
Some hardware vendors, notablyIBM andLenovo, use the termmicrocode interchangeably with embeddedfirmware. In this context, all code within a device is termed microcode, whether it is microcode or machine code. For instance, updates to ahard disk drive's microcode may encompass updates to both its microcode and firmware.[63] Embedded firmware has been popular in application-specific processors such asnetwork processors,digital signal processors,channel controllers,disk controllers,network interface controllers,flash memory controllers,graphics processing units, and in other hardware.
4096 x 75-bit SRAM writable control store: 74-bit microinstruction with 1 parity bit (18 fields)
{{cite book}}: CS1 maint: location (link)