Ametal gate, in the context of a lateralmetal–oxide–semiconductor (MOS) stack, is the gate electrode separated by an oxide from the transistor's channel – the gate material is made from a metal. In most MOS transistors since about the mid-1970s, the "M" for metal has been replaced bypolysilicon, but the name remained.
The firstMOSFET (metal–oxide–semiconductor field-effect transistor) was made byMohamed Atalla andDawon Kahng atBell Labs in 1959, and demonstrated in 1960.[1] They usedsilicon as channel material and a non-self-alignedaluminum gate.[2] Aluminum gate metal (typically deposited in an evaporation vacuum chamber onto the wafer surface) was common through the early 1970s.
By the late 1970s, the industry had moved away from aluminum as the gate material in themetal–oxide–semiconductor stack due to fabrication complications and performance issues.[citation needed] A material calledpolysilicon (polycrystallinesilicon, highlydoped with donors or acceptors to reduce its electrical resistance) was used to replacealuminum.
Polysilicon can be deposited easily viachemical vapor deposition (CVD) and is tolerant to subsequent manufacturing steps which involve extremely high temperatures (in excess of 900–1000 °C), where metal was not. Particularly, metal (most commonlyaluminum – a Type III (P-type) dopant) has a tendency to disperse into (alloy with) silicon during thesethermal annealing steps.[3][4] In particular, when used on asilicon wafer with a < 1 1 1 > crystal orientation, excessive alloying of aluminum (from extended high temperature processing steps) with the underlying silicon can create ashort circuit between the diffused FETsource or drain areas under the aluminum and across the metallurgical junction into the underlying substrate – causing irreparable circuit failures. These shorts are created by pyramidal-shaped spikes ofsilicon-aluminumalloy – pointing vertically "down" into thesilicon wafer. The practical high-temperature limit for annealingaluminum on silicon is on the order of 450 °C.Polysilicon is also attractive for the easy manufacturing ofself-aligned gates. The implantation or diffusion of source and drain dopant impurities is carried out with the gate in place, leading to a channel perfectly aligned to the gate without additionallithographic steps with the potential for misalignment of the layers.
InNMOS andCMOS technologies, over time and elevated temperatures, the positive voltages employed by the gate structure can cause any existing positively chargedsodium impurities directly under the positively charged gate to diffuse through the gate dielectric and migrate to the less-positively-charged channel surface, where the positivesodium charge has a higher effect on the channel creation – thus lowering thethreshold voltage of an N-channel transistor and potentially causing failures over time. EarlierPMOS technologies were not sensitive to this effect because the positively charged sodium was naturally attracted towards the negatively charged gate, and away from the channel, minimizing threshold voltage shifts. N-channel, metal gate processes (in the 1970s) imposed a very high standard of cleanliness (absence ofsodium) – difficult to achieve in that timeframe, resulting in high manufacturing costs.Polysilicon gates – while sensitive to the same phenomenon, could be exposed to small amounts ofHCl gas during subsequent high-temperature processing (commonly called "gettering") to react with anysodium, binding with it to form NaCl and carrying it away in the gas stream, leaving an essentially sodium-free gate structure – greatly enhancing reliability.
However,polysilicon doped at practical levels does not offer the near-zeroelectrical resistance of metals, and is therefore not ideal for charging and discharging thegate capacitance of thetransistor – potentially resulting in slower circuitry.
From the45 nm node onward, the metal gate technology returns, together with the use of high-dielectric (high-κ) materials, pioneered by Intel developments.
The candidates for the metal gate electrode are, for NMOS, Ta, TaN, Nb (single metal gate) and for PMOS WN/RuO2 (the PMOS metal gate is normally composed by two layers of metal). Due to this solution, the strain capacity on the channel can be improved (by the metal gate). Moreover, this enables less current perturbations (vibrations) in the gate (due to the disposition of electrons inside the metal).
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