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Memory hierarchy

From Wikipedia, the free encyclopedia
Computer memory architecture
Diagram of the computer memory hierarchy
Computer memory anddata storage types
General
Volatile
Historical
Non-volatile
Not to be confused withLearning pyramid.

Incomputer architecture, thememory hierarchy separatescomputer storage into a hierarchy based onresponse time. Since response time,complexity, andcapacity are related, the levels may also be distinguished by theirperformance and controlling technologies.[1] Memory hierarchy affects performance in computer architectural design, algorithm predictions, and lower levelprogramming constructs involvinglocality of reference.

Designing for high performance requires considering the restrictions of the memory hierarchy, i.e. the size and capabilities of each component. Each of the various components can be viewed as part of a hierarchy of memories(m1,m2, ...,mn) in which each membermi is typically smaller and faster than the next highest membermi+1 of the hierarchy. To limit waiting by higher levels, a lower level will respond by filling a buffer and then signaling for activating the transfer.

There are four major storage levels.[1]

  • Internal – processor registers andcache.
  • Main – the systemRAM and controller cards.
  • On-line mass storage – secondary storage.
  • Off-line bulk storage – tertiary and off-line storage.

This is a general memory hierarchy structuring. Many other structures are useful. For example, a paging algorithm may be considered as a level forvirtual memory when designing acomputer architecture, and one can include a level ofnearline storage between online and offline storage.

Properties of the technologies in the memory hierarchy

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  • Adding complexity slows thememory hierarchy.[2]
  • CMOx memory technology stretches the flash space in the memory hierarchy[3]
  • One of the main ways to increase system performance is minimising how far down the memory hierarchy one has to go to manipulate data.[4]
  • Latency and bandwidth are two metrics associated with caches. Neither of them is uniform, but is specific to a particular component of the memory hierarchy.[5]
  • Predicting where in the memory hierarchy the data resides is difficult.[5]
  • The location in the memory hierarchy dictates the time required for the prefetch to occur.[5]

Examples

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Memory hierarchy of an AMD Bulldozer server as detected byhwloc'slstopo tool

The number of levels in the memory hierarchy and the performance at each level has increased over time. The type of memory or storage components also change historically.[6]

Cache, memory, and external storage hierarchy of a 2020s computer system (AMDZen 4)
LevelSizeThroughputLatencyNotes
Register file18,432 bitsUp to 256 GB/s (512 bits/cycle)0.25 ns (1 cycle)[7]All CPU-related conversion assumes a 4.0 GHz clock. Same for below. Full utilization of throughput is impossible on real workloads. Size is provided for each core.
CPU cacheL1 data32 KiBUp to 64 GB/s (64 bytes/4 cycles)1 ns (4 cycles)[7]Hardware prefetching is required for maximum throughput. Size and throughput are per-core. Code cache has the same size but is not manipulable as data.
L21 MBUp to 18.3 GB/s (64 bytes/14 cycles)3.5 ns (14 cycles)[7]Size and throughput are per-core.
L316–32 MBUp to 5.45 GB/s (64 bytes/47 cycles)11.75 ns (47 cycles)[7]Size is shared among 8 cores. Throughput is per-core.
Main memory (primary)64 GiB~60 GB/s82.5 nsSize is shared among all cores. Latency depends on the memory clock and memory timings. In this case, a result from a pair of 32 GB DDR5 DIMMs set to 6000 MT/s via the factory EXPO profile is used.[8]

Systems with multiple CPU sockets have an additionalNUMA delay when a CPU tries to access memory under the control of another NUMA node.

Mass storage
(secondary)
Solid-state drive2 TB2000 MB/s0.2 msFigures for aM.2NVMe SSD from 2017, the Samsung 960 Pro.[9]
Hard disk drive18 TB500 MB/s4.16 msPer-drive figures for Exos 2X18 (ST18000NM0092), an enterprise-grade 3.5 inch SATA HDD.[10]
Nearline
(tertiary)
Spun-down HDDs (MAID)Petabytes25 sPer-drive figures for Exos 2X18 (ST18000NM0092), from user manual entry for "start/stop times".[11] In a typical MAID setup, hundreds of spun-down HDDs may be used for petabytes of storage.
Tape libraryExabytes160 MB/s[12]Minutes
Offline storageExabytesDepends on mediumDepends on human operation

Some CPUs include additional levels of cache between L3 and memory. For example, theHaswell microarchitecture includes an L4 cache of 128 MB on mobile units.[13][14]

The lower levels of the hierarchy – from mass storage downwards – are also known astiered storage. The formal distinction between online, nearline, and offline storage is:[15]

  • Online storage is immediately available for I/O.
  • Nearline storage is not immediately available, but can be made online quickly without human intervention.
  • Offline storage is not immediately available, and requires some human intervention to bring online.

For example, always-on spinning disks are online, while spinning disks that spin down, such as massive arrays of idle disk (MAID), are nearline. Removable media such as tape cartridges that can be automatically loaded, as in atape library, are nearline, while cartridges that must be manually loaded are offline.

Programming

[edit]

Most modernCPUs are so fast that, for most program workloads, thebottleneck is thelocality of reference of memory accesses and the efficiency of thecaching and memory transfer between different levels of the hierarchy[citation needed]. As a result, the CPU spends much of its time idling, waiting for memory I/O to complete. This is sometimes called thespace cost, as a larger memory object is more likely to overflow a small and fast level and require use of a larger, slower level. The resulting load on memory use is known aspressure (respectivelyregister pressure,cache pressure, and (main)memory pressure). Terms for data being missing from a higher level and needing to be fetched from a lower level are, respectively:register spilling (due toregister pressure: register to cache),cache miss (cache to main memory), and (hard)page fault (real main memory tovirtual memory, i.e. mass storage, commonly referred to asdisk regardless of the actual mass storage technology used).

Modernprogramming languages mainly assume two levels of memory, main (working) memory and mass storage. The exception is the relatively low-levelassembly language and in theinline assemblers of higher-level languages such asC. Taking optimal advantage of the memory hierarchy requires the cooperation of programmers, hardware, and compilers (as well as underlying support from the operating system):

  • Programmers are responsible for moving data between disk and memory through file I/O.
  • Hardware is responsible for moving data between memory and caches.
  • Optimizing compilers are responsible for generating code that, when executed, will cause the hardware to use caches and registers efficiently.

Many programmers assume one level of memory. This works fine until the application hits a performance wall. At that point, the programmer needs to change the code's memory access patterns to that it works well with cache resources. A classic illustration of the effect of locality and caching is in the form of changing the order of iterating a three-dimensional array.Computer Systems: A Programmer's Perspective is a classic textbook that deals with this aspect of systems programming.[16]

See also

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References

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  1. ^abToy, Wing; Zee, Benjamin (1986).Computer Hardware/Software Architecture. Prentice Hall. p. 30.ISBN 0-13-163502-6.
  2. ^Write-combining
  3. ^"Memory Hierarchy". Unitity Semiconductor Corporation. Archived fromthe original on 5 August 2009. Retrieved16 September 2009.
  4. ^Pádraig Brady."Multi-Core". Retrieved16 September 2009.
  5. ^abcvan der Pas, Ruud (2002)."Memory Hierarchy in Cache-Based Systems"(PDF). Santa Clara, California:Sun Microsystems: 26. 817-0742-10.{{cite journal}}:Cite journal requires|journal= (help)
  6. ^"Memory & Storage – Timeline of Computer History – Computer History Museum".www.computerhistory.org.
  7. ^abcdFog, Agner."The microarchitecture of Intel and AMD CPUs"(PDF). Chapters used: 24.16 Cache and memory access (Zen 4).
  8. ^"AMD Ryzen 7000/9000 DDR5 RAM OC Guide XPM and EXPO Profile Benchmarks".
  9. ^"Samsung 960 Pro M.2 NVMe SSD Review". storagereview.com. 20 October 2016. Retrieved2017-04-13.
  10. ^"Datasheet Exos 2X18"(PDF).
  11. ^"2X18 SATA Product Manual"(PDF).
  12. ^"Ultrium – LTO Technology – Ultrium GenerationsLTO". Lto.org. Archived fromthe original on 2011-07-27. Retrieved2014-07-31.
  13. ^Crothers, Brooke."Dissecting Intel's top graphics in Apple's 15-inch MacBook Pro – CNET". News.cnet.com. Retrieved2014-07-31.
  14. ^"SiSoftware Zone". Sisoftware.co.uk. Archived fromthe original on 2014-09-13. Retrieved2014-07-31.
  15. ^Pearson, Tony (2010)."Correct use of the term Nearline".IBM Developerworks, Inside System Storage. Archived fromthe original on 2018-11-27. Retrieved2015-08-16.
  16. ^"A Programmer's Perspective: Memory Systems".
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