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Amemory controller, also known asmemory chip controller (MCC) or amemory controller unit (MCU), is a digital circuit that manages the flow of data going to and from a computer'smain memory.[1][2] When a memory controller is integrated into another chip, such as an integral part of amicroprocessor, it is usually called anintegrated memory controller (IMC).
Memory controllers contain the logic necessary to read and write todynamic random-access memory (DRAM), and to provide the criticalmemory refresh and other functions. Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to themultiplexer circuit, where thedemultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the requiredbus width for the operation. Memory controllers' bus widths range from8-bit in earlier systems, to 512-bit in more complicated systems, where they are typically implemented as four64-bit simultaneous memory controllers operating in parallel, though some operate with two 64-bit memory controllers being used to access a128-bit memory device.
Some memory controllers, such as the one integrated intoPowerQUICC II processors, includeerror detection and correction hardware.[3] Many modern processors are also integratedmemory management unit (MMU), which in manyoperating systems implementsvirtual addressing. On early x86-32 processors, the MMU is integrated in the CPU, but the memory controller is usually part ofnorthbridge.[4]
Older Intel andPowerPC-based computers have memory controller chips that are separate from the main processor. Often these are integrated into thenorthbridge of the computer, also sometimes called a memory controller hub.
Most modern desktop or workstation microprocessors use anintegrated memory controller (IMC), including microprocessors fromIntel,AMD, and those built around theARM architecture. Prior toK8 (circa 2003),AMD microprocessors had a memory controller implemented on their motherboard'snorthbridge. In K8 and later, AMD employed an integrated memory controller.[5] Likewise, untilNehalem (circa 2008),Intel microprocessors used memory controllers implemented on the motherboard's northbridge. Nehalem and later switched to an integrated memory controller.[6] Other examples of microprocessor architectures that useintegrated memory controllers includeNVIDIA'sFermi,IBM'sPOWER5, andSun Microsystems'sUltraSPARC T1.
While an integrated memory controller has the potential to increase the system's performance, such as by reducingmemory latency, it locks the microprocessor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. WhenDDR2 SDRAM was introduced, AMD released newAthlon 64 CPUs. These new models, with a DDR2 controller, use a different physical socket (known asSocket AM2), so that they will only fit in motherboards designed for the new type of RAM. When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge to use newer memory.
Some microprocessors in the 1990s, such as the DECAlpha 21066 and HPPA-7300LC, had integrated memory controllers; however, rather than for performance gains, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.[citation needed]
Some CPUs are designed to have their memory controllers as dedicated external components that are not part of the chipset. An example is IBMPOWER8, which uses externalCentaur chips that are mounted ontoDIMM modules and act as memory buffers,L4 cache chips, and as the actual memory controllers. The first version of the Centaur chip used DDR3 memory but an updated version was later released which can use DDR4.[7]
A few experimental memory controllers contain a second level of address translation, in addition to the first level of address translation performed by the CPU'smemory management unit to improve cache and bus performance.[8]
Memory controllers integrated into certainIntel Core processors providememory scrambling as a feature that turns user data written to the main memory intopseudo-random patterns.[9][10] Memory scrambling has the potential to preventforensic andreverse-engineering analysis based onDRAM data remanence by effectively rendering various types ofcold boot attacks ineffective. In current practice, this has not been achieved; memory scrambling has only been designed to address DRAM-related electrical problems. The late 2010s memory scrambling standards do address security issues and are not cryptographically secure or open to public revision or analysis.[11]
ASUS and Intel have their separate memory scrambling standards. ASUS motherboards have allowed the user to choose which memory scrambling standard to use (ASUS or Intel) or whether to turn the feature off entirely.[citation needed]
Double data rate (DDR) memory controllers are used to driveDDR SDRAM, where data is transferred on both rising and falling edges of the system's memory clock. DDR memory controllers are significantly more complicated when compared to single data rate controllers,[citation needed] but they allow for twice the data to be transferred without increasing the memory's clock rate or bus width.
Multichannel memory controllers are memory controllers where the DRAM devices are separated onto multiple buses to allow the memory controller(s) to access them in parallel. This increases the theoretical amount of bandwidth of the bus by a factor of the number of channels. While a channel for every DRAM would be the ideal solution, adding more channels increases complexity and cost.
Fully buffered memory systems place a memory buffer device on everymemory module (called anFB-DIMM when fully buffered RAM is used), which unlike traditional memory controller devices, use a serial data link to the memory controller instead of the parallel link used in previous RAM designs. This decreases the number of wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard.
Manyflash memory devices, such asUSB flash drives andsolid-state drives, include aflash memory controller. Flash memory is inherently slower to access than RAM and often becomes unusable after a few million write cycles, which generally makes it unsuitable for RAM applications.
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