Thememory cell is the fundamental building block ofcomputer memory. The memory cell is a device, such as anelectronic circuit, that stores onebit of binary information and it must be set to store a logic 1 (highvoltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

Over thehistory of computing, different memory cell architectures have been used, includingcore memory,twistor memory,^[1] andbubble memory. Today^{[as of?]}, the most common memory cell architecture isMOS memory, which consists ofmetal–oxide–semiconductor (MOS) memory cells. Modernrandom-access memory (RAM) usesMOS field-effect transistors (MOSFETs) as flip-flops, along withMOS capacitors for certain types of RAM.

The SRAM (static RAM) memory cell is a type offlip-flop circuit, typically implemented using MOSFETs. These require very low power to maintain the stored value when not being accessed. A second type, DRAM (dynamic RAM), is based on MOS capacitors. Charging and discharging a capacitor can store either a '1' or a '0' in the cell. However, since the charge in the capacitor slowly dissipates, it must be refreshed periodically. Due to this refresh process, DRAM consumes more power, but it can achieve higher storage densities.

Mostnon-volatile memory (NVM), on the other hand, is based onfloating-gate memory cell architectures. Non-volatile memory technologies such asEPROM,EEPROM, andflash memory utilize floating-gate memory cells, which rely onfloating-gate MOSFET transistors.

The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such asbipolar,MOS, and othersemiconductor devices. It can also be built frommagnetic material such asferrite cores or magnetic bubbles.^[2] Regardless of the implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0.^[3]

Logic circuits without memory cells are calledcombinational, meaning the output depends only on the present input.

But memory is a key element ofdigital systems. In computers, it allows to store both programs and data and memory cells are also used for temporary storage of the output of combinational circuits to be used later by digital systems.

Logic circuits that use memory cells are calledsequential circuits, meaning the output depends not only on the present input, but also on the history of past inputs.This dependence on the history of past inputs makes these circuitsstateful and it is the memory cells that store this state. These circuits require a timing generator or clock for their operation.^[4]

Computer memory used in most contemporarycomputer systems is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That is the reason why SRAM memory is used for on-chipcache included in modernmicroprocessor chips.^[5]

On December 11, 1946Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device (Williams tube) with 128 40-bit words. It was operational in 1947 and is considered the first practical implementation ofrandom-access memory (RAM).^[6] In that year, the first patent applications formagnetic-core memory were filed by Frederick Viehe.^[7][8] Practical magnetic-core memory was developed byAn Wang in 1948, and improved byJay Forrester andJan A. Rajchman in the early 1950s, before being commercialised with theWhirlwind computer in 1953.^[9]Ken Olsen also contributed to its development.^[10]

Semiconductor memory began in the early 1960s with bipolar memory cells, made ofbipolar transistors. While it improved performance, it could not compete with the lower price of magnetic-core memory.^[11]

In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.^[12] Subsequently, a team demonstrated a workingMOSFET at Bell Labs 1960.^[13][14] The invention of the MOSFET enabled the practical use ofmetal–oxide–semiconductor (MOS) transistors as memory cell storage elements, a function previously served bymagnetic cores.^{[citation needed]}

The first modern memory cells were introduced in 1964, when John Schmidt designed the first 64-bit p-channel MOS (PMOS)static random-access memory (SRAM).^[15][16]

SRAM typically has six-transistor cells, whereasDRAM (dynamic random-access memory) typically has single-transistor cells.^[17][15] In 1965,Toshiba's Toscal BC-1411electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting ofgermanium bipolar transistors and capacitors.^[18][19] MOS technology is the basis for modern DRAM. In 1966,Robert H. Dennard at theIBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of buildingcapacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.^[20] In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology.^[21]

The first commercial bipolar 64-bitSRAM was released byIntel in 1969 with the 3101SchottkyTTL. One year later, it released the first DRAMintegrated circuit chip, theIntel 1103, based on MOS technology. By 1972, it beat previous records insemiconductor memory sales.^[22] DRAM chips during the early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s.^[17][15]

CMOS memory was commercialized byRCA, which launched a 288-bit CMOS SRAM memory chip in 1968.^[23] CMOS memory was initially slower thanNMOS memory, which was more widely used by computers in the 1970s.^[24] In 1978,Hitachi introduced the twin-well CMOS process, with its HM6147 (4 kb SRAM) memory chip, manufactured with a3 μm process. The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most commonsemiconductor manufacturing process for computer memory in the 1980s.^[24]

The two most common types of DRAM memory cells since the 1980s have been trench-capacitor cells and stacked-capacitor cells.^[25] Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure.^[26] Both debuted in 1984, when Hitachi introduced trench-capacitor memory andFujitsu introduced stacked-capacitor memory.^[25]

Thefloating-gate MOSFET (FGMOS) was invented byDawon Kahng andSimon Sze atBell Labs in 1967.^[27] They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to producereprogrammable ROM (read-only memory).^[28] Floating-gate memory cells later became the basis fornon-volatile memory (NVM) technologies includingEPROM (erasable programmable ROM),EEPROM (electrically erasable programmable ROM) andflash memory.^[29]

Flash memory was invented byFujio Masuoka atToshiba in 1980.^[30][31] Masuoka and his colleagues presented the invention ofNOR flash in 1984,^[32] and thenNAND flash in 1987.^[33]Multi-level cell (MLC) flash memory was introduced byNEC, which demonstratedquad-level cells in a 64 Mb flash chip storing 2-bit per cell in 1996.^[25] 3DV-NAND, where flash memory cells are stacked vertically using 3Dcharge trap flash (CTP) technology, was first announced by Toshiba in 2007,^[34] and first commercially manufactured bySamsung Electronics in 2013.^[35][36]

The following schematics detail the three most used implementations for electronic memory cells:

• The dynamic random access memory cell (DRAM);
• The static random access memory cell (SRAM);
• Flip-flops like the J/K shown below, using onlylogic gates.

The storage element of theDRAM memory cell is thecapacitor labeled (4) in the diagram above. The charge stored in the capacitor degrades over time, so its value must be refreshed (read and rewritten) periodically. ThenMOS transistor (3) acts as a gate to allow reading or writing when open or storing when closed.^[37]

For reading the word line (2) drives a logic 1 (voltage high) into the gate of thenMOS transistor (3) which makes it conductive and the charge stored at the capacitor (4) is then transferred to the bit line (1). The bit line will have aparasitic capacitance (5) that will drain part of the charge and slow the reading process. The capacitance of the bit line will determine the needed size of the storage capacitor (4). It is a trade-off. If the storage capacitor is too small, the voltage of the bit line would take too much time to raise or not even rise above the threshold needed by the amplifiers at the end of the bit line. Since the reading process degrades the charge in the storage capacitor (4) its value is rewritten after each read.^[38]

The writing process is the easiest, the desired value logic 1 (high voltage) or logic 0 (low voltage) is driven into the bit line. The word line activates thenMOS transistor (3) connecting it to the storage capacitor (4). The only issue is to keep it open enough time to ensure that the capacitor is fully charged or discharged before turning off the nMOS transistor (3).^[38]

The working principle ofSRAM memory cell can be easier to understand if the transistors M1 through M4 are drawn aslogic gates. That way it is clear that at its heart, the cell storage is built by using two cross-coupledinverters. This simple loop creates a bi-stable circuit. A logic 1 at the input of the first inverter turns into a 0 at its output, and it is fed into the second inverter which transforms that logic 0 back to a logic 1 feeding back the same value to the input of the first inverter. That creates a stable state that does not change over time. Similarly the other stable state of the circuit is to have a logic 0 at the input of the first inverter. After being inverted twice it will also feedback the same value.^[39]

Therefore there are only two stable states that the circuit can be in:

• ${\displaystyle Q}$ = 0 and  ${\displaystyle \overline{Q}}$ = 1
• ${\displaystyle Q}$ = 1 and  ${\displaystyle \overline{Q}}$ = 0

To read the contents of the memory cell stored in the loop, the transistors M5 and M6 must be turned on. when they receive voltage to their gates from the word line (${\displaystyle WL}$), they become conductive and so the${\displaystyle Q}$ and  ${\displaystyle \overline{Q}}$  values get transmitted to the bit line (${\displaystyle BL}$) and to its complement (${\displaystyle \overline{BL}}$).^[39] Finally this values get amplified at the end of the bit lines.^[39]

The writing process is similar, the difference is that now the new value that will be stored in the memory cell is driven into the bit line (${\displaystyle BL}$) and the inverted one into its complement (${\displaystyle \overline{BL}}$). Next transistors M5 and M6 are open by driving a logic 1 (voltage high) into the word line (${\displaystyle WL}$). This effectively connects the bit lines to the by-stable inverter loop. There are two possible cases:

1. If the value of the loop is the same as the new value driven, there is no change;
2. if the value of the loop is different from the new value driven there are two conflicting values, in order for the voltage in the bit lines to overwrite the output of the inverters, the size of the M5 and M6 transistors must be larger than that of the M1-M4 transistors. This allows more current to flow through first ones and therefore tips the voltage in the direction of the new value, at some point the loop will then amplify this intermediate value to full rail.^[39]

Theflip-flop has many different implementations, its storage element is usually a latch consisting of aNAND gate loop or aNOR gate loop with additional gates used to implement clocking. Its value is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented usingMOSFETs; they have also been implemented usingbipolar transistors.

Floating-gate memory cells, based onfloating-gate MOSFETs, are used for mostnon-volatile memory (NVM) technologies, includingEPROM,EEPROM andflash memory.^[29] According to R. Bez and A. Pirovano:

A floating-gate memory cell is basically anMOS transistor with a gate completely surrounded bydielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from the CG) of the cell transistor.^[29]

• Dynamic random-access memory
• Flip-flop (electronics)
• Row hammer
• Static random-access memory

• Computer memory
• Digital electronics
• Digital systems
• Electronic engineering
• MOSFETs

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