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| Industry | Computers |
|---|---|
| Founded | 1987; 39 years ago (1987) inSunnyvale, California, United States |
| Founder | Jeff Kalb |
| Defunct | 1999 (1999) |
| Fate | Acquired byAccrue Software |
| Website | neovista.com at theWayback Machine (archived 1997-10-16) |
MasPar Computer Corporation (laterNeoVista Software, Inc.) was aminisupercomputer vendor that was founded in 1987 by Jeff Kalb. The company was based inSunnyvale, California.
While Kalb was the vice-president of the division ofDigital Equipment Corporation (DEC) that builtintegrated circuits, some researchers in that division were building a supercomputer based on theGoodyear MPP (massively parallel processor) supercomputer. The DEC researchers enhanced the architecture by:
After Digital decided not to commercialize the research project, Kalb decided to start a company to sell this minisupercomputer. In 1990, the first generation product MP-1 was delivered. In 1992, the follow-on MP-2 was shipped. The company shipped more than 200 systems.
MasPar along withnCUBE criticized the open government support, byDARPA, of competitorsIntel for their hypercube Personal SuperComputers (iPSC) and theThinking MachinesConnection Machine on the pages ofDatamation.
Samples of MasPar MPs, from theNASAGoddard Space Flight Center, are in storage at theComputer History Museum.
MasPar offered a family ofSIMD machines, second sourced by DEC. The processor units are proprietary.
There was no MP-3. MasPar exited the computer hardware business in June 1996, halting all hardware development and transforming itself into a newdata mining software company calledNeoVista Software. NeoVista was acquired byAccrue Software in 1999, which in turn sold the division toJDA Software in 2001.[2][3]
MasPar is unique in being a manufacturer ofSIMD supercomputers (as opposed to vector machines). In this approach, a collection ofALU's listen to a program broadcast from a central source. The ALUs can do their own data fetch, but are all under control of a central Array Control Unit. There is a central clock. The emphasis is on communications efficiency, and low latency. The MasPar architecture is designed to scale, and balance processing, memory, and communication.
The Maspar MP-1 PE and the later binary-compatible Maspar MP-2 PE arefull customCMOS chips, designed in-house,[1] and fabricated by various vendors such asHP orTI.
The Array Control Unit (ACU) handles instruction fetch. It is aload-store architecture. The MasPar architecture isHarvard in a broad sense. The ACU implements amicrocoded instruction fetch, but achieves a RISC-like 1 instruction per clock. The Arithmetic units, ALUs with data fetch capability, are implemented 32 to a chip. Each ALU is connected in a nearest neighbor fashion to 8 others. The edge connections are brought off-chip. In this scheme, the perimeters can betoroid-wrapped. Up to 16,384 units can be connected within the confines of a cabinet. A global router, essentially across-bar switch, provides external I/O to the processor array.
The MP-2 PE chip contains 32 processor elements, each a full 32-bit ALU with floating point,registers, and abarrel shifter. Only the instruction fetch feature is removed, and placed in the ACU. The PE design is literally replicated 32 times on the chip. The chip is designed to interface toDRAM, to other processor array chips, and to communication router chips.
Each ALU, called a PE slice, contains 64 × 32 bit registers that are used for both integer and floating point. The registers are both bit andbyte addressable. The floating point unit handlessingle precision anddouble precision arithmetic onIEEE format numbers. Each PE slice contains two registers for data memory address, and the data. Each PE also has two one-bit serial ports, one for inbound and one for outbound communication to its nearest neighbor. The direction of communication is controlled globally. The PEs also have inbound and outbound paths to a global router for I/O. A broadcast port allows a single instance of data to be "promoted" to parallel data. Alternately, global data can be 'or-ed' to a scalar result.
The serial links support 1 Mbyte/sbit-serial communication that allows coordinated register-register communication between processors. Each processor has its own local memory, implemented in DRAM. No internal memory is included on the processors. Microcoded instruction decode is used.
The 32 PEs on a chip are clustered into two groups sharing a common memory interface, or M-machine, for access. A global scoreboard keeps track of memory and register usage. The path to memory is 16 bits wide. Both big and little endian formats are supported. Each processor has its own 64 Kbyte of memory. Both direct and indirect data memory addressing are supported.
The chip is implemented in 1.0-micrometre, two-level, metal CMOS, dissipates 0.8 watt, and is packaged in a 208-pinPQFP. A relatively low clock rate of 12.5 MHz is used.
The Maspar machines are front ended by a host machine, usually aVAX. They are accessed by extensions toFortran andC. Full IEEE single- and double-precision floating point are supported.
There is no cache for the ALUs. Cache is not required, due to the memory interface operating at commensurate speed with the ALU data accesses.
The ALUs do not implementmemory management for data memory. The ACU uses demand pagedvirtual memory for the instruction memory.
As a gimmick MasPar handed out business cards with an MP-2 PE chip laminated to them.