TheMC88100 is amicroprocessor developed byMotorola that implemented88000RISCinstruction set architecture. Announced in 1988, the MC88100 was the first 88000 implementation. It was succeeded by theMC88110 in the early 1990s.
The microprocessor has separate pipelined integer, floating-point add, floating-point multiply, and load/store execution units and dispatches a single instruction (at most) per clock cycle. The separate MC88200integrated circuit optionally add level 1 cache and a pagedmemory management unit. An MC88100 system typically used two of these devices for instructions and data; additional MC88200s could be added to increase the size of the caches.
This partitioned scheme was chosen to provide system flexibility, the amount of cache could be varied depending on the price point. In practice, these additional chips required more space on the circuit board and the buses between the MC88200s and MC88100 added complexity and cost.
The MC88100 contained 165,000 transistors and the MC88200 750,000 transistors. Both were fabricated by Motorola in its 1.5 μmcomplementary metal–oxide–semiconductor process.
The MC88100 was ultimately commercially unsuccessful.[citation needed] This was due to a number of reasons, including requirement of MC88200s in most cases[a], but was mostly due to Motorola being a vendor of the highly successful68000 family. As the 68000 division viewed the 88000 as a competitor, they forced the MC88100 to be priced unacceptably high for a volume part.[citation needed] The part did find use in the high-end embedded market, in Motorola's own computers, and in large computers from companies such asData General and theUnisys S-8400 Unix Servers.
The programming model and register set of the MC88100 is remarkably similar toDLX (and by extension,RISC-V) based CPUs, with 32General-purpose registers (31 writable) and 51 instructions capable of accessing any of the 32 general-purpose registers at any time.
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The MC88100 is equipped with a total of 64 user-accessible registers, 32 of them beingControl registers, and can access up to 6 registers (4 read, 2 write) simultaneously. The actual usage of GPR is not enforced by the processor for every register except R1, which is used as a return address.
