Alogic gate is a device that performs aBoolean function, alogical operation performed on one or morebinary inputs that produces a single binary output. Depending on the context, the term may refer to anideal logic gate, one that has, for instance, zerorise time and unlimitedfan-out, or it may refer to a non-ideal physical device[1] (seeideal and real op-amps for comparison).
Logic gates can be cascaded in the same way that Boolean functions can be composed, allowing the construction of a physical model of all ofBoolean logic, and therefore, all of the algorithms andmathematics that can be described with Boolean logic.Logic circuits include such devices asmultiplexers,registers,arithmetic logic units (ALUs), andcomputer memory, all the way up through completemicroprocessors,[5] which may contain more than 100 million logic gates.
Compound logic gatesAND-OR-Invert (AOI) andOR-AND-Invert (OAI) are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.[6]
From 1934 to 1936,NEC engineerAkira Nakashima,Claude Shannon andVictor Shestakov introducedswitching circuit theory in a series of papers showing thattwo-valuedBoolean algebra, which they discovered independently, can describe the operation of switching circuits.[12][13][14][15] Using this property of electrical switches to implement logic is the fundamental concept that underlies all electronic digitalcomputers. Switching circuit theory became the foundation ofdigital circuit design, as it became widely known in the electrical engineering community during and afterWorld War II, with theoretical rigor superseding thead hoc methods that had prevailed previously.[15]
In 1948,Bardeen andBrattain patented an insulated-gate transistor (IGFET) with an inversion layer. Their concept forms the basis of CMOS technology today.[16] In 1957 Frosch and Derick were able to manufacturePMOS andNMOS planar gates.[17] Later a team at Bell Labs demonstrated a working MOS with PMOS and NMOS gates.[18] Both types were later combined and adapted intocomplementary MOS (CMOS) logic byChih-Tang Sah andFrank Wanlass atFairchild Semiconductor in 1963.[19]
A synchronous 4-bit up/downdecade counter symbol (74LS192) in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 60617-12.
There are two sets of symbols for elementary logic gates in common use, both defined inANSI/IEEE Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings and derives fromUnited States Military Standard MIL-STD-806 of the 1950s and 1960s.[20] It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on ANSI Y32.14 and other early industry standards as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.[21] The IEC standard,IEC 60617-12, has been adopted by other standards, such asEN 60617-12:1999 in Europe,BS EN 60617-12:1999 in the United Kingdom, andDIN EN 60617-12:1998 in Germany.
The mutual goal of IEEE Std 91-1984 and IEC 617-12 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium-scale circuits such as a 4-bit counter to a large-scale circuit such as a microprocessor.
IEC 617-12 and its renumbered successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.[21] These are, however, shown in ANSI/IEEE Std 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." IEC 60617-12 correspondingly contains the note (Section 2.1) "Although non-preferred, the use of other symbols recognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shall not be considered to be in contradiction with this standard. Usage of these other symbols in combination to form complex symbols (for example, use as embedded symbols) is discouraged." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another.
In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called abubble and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that thepositive logic convention ornegative logic convention is being used (high voltage level = 1 or low voltage level = 1, respectively). Thewedge is used in circuit diagrams to directly indicate an active-low (low voltage level = 1) input or output without requiring a uniform convention throughout the circuit diagram. This is calledDirect Polarity Indication. See IEEE Std 91/91A and IEC 60617-12. Both thebubble and thewedge can be used on distinctive-shape andrectangular-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only thebubble is meaningful.
The output of a two input exclusive-OR is true only when the two input values aredifferent, and false if they are equal, regardless of the value. If there are more than two inputs, the output of the distinctive-shape symbol is undefined. The output of the rectangular-shaped symbol is true if the number of true inputs is exactly one or exactly the number following the "=" in the qualifying symbol.
By use ofDe Morgan's laws, anAND function is identical to anOR function with negated inputs and outputs. Likewise, anOR function is identical to anAND function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs.
This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND orOR) but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams – thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated.
A De Morgan symbol can show more clearly a gate's primary logical purpose and the polarity of its nodes that are considered in the "signaled" (active, on) state. Consider the simplified case where a two-input NAND gate is used to drive a motor when either of its inputs are brought low by a switch. The "signaled" state (motor on) occurs when either one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morgan version, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubble at the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbol shows both inputs and output in the polarity that will drive the motor.
De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons.
Logic gates can also be used to hold a state, allowing data storage. A storage element can be constructed by connecting several gates in a "latch" circuit. Latching circuitry is used instatic random-access memory. More complicated designs that useclock signals and that change only on a rising or falling edge of the clock are called edge-triggered "flip-flops". Formally, a flip-flop is called abistable circuit, because it has two stable states which it can maintain indefinitely. The combination of multiple flip-flops in parallel, to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called asequential logic system since its output can be influenced by its previous state(s), i.e. by thesequence of input states. In contrast, the output fromcombinational logic is purely a combination of its present inputs, unaffected by the previous input and output states.
These logic circuits are used in computermemory. They vary in performance, based on factors ofspeed, complexity, and reliability of storage, and many different types of designs are used based on the application.
Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-gainvoltageamplifier, which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate.
The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.
For small-scale logic, designers now use prefabricated logic gates from families of devices such as theTTL7400 series byTexas Instruments, theCMOS4000 series byRCA, and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced byprogrammable logic devices, which allow designers to pack many mixed logic gates into a single integrated circuit. The field-programmable nature ofprogrammable logic devices such asFPGAs has reduced the 'hard' property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed.
An important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each integrated circuit are considered.
The output of one gate can only drive a finite number of inputs to other gates, a number called the 'fan-out limit'. Also, there is always a delay, called the 'propagation delay', from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speedsynchronous circuits. Additional delay can be caused when many inputs are connected to an output, due to the distributedcapacitance of all the inputs and wiring and the finite amount of current that each output can provide.
There are severallogic families with different characteristics (power consumption, speed, cost, size) such as:RDL (resistor–diode logic),RTL (resistor-transistor logic),DTL (diode–transistor logic),TTL (transistor–transistor logic) and CMOS. There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slower PMOS transistors.
The simplest family of logic gates usesbipolar transistors, and is calledresistor–transistor logic (RTL). Unlike simple diode logic gates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logic functions. RTL gates were used in earlyintegrated circuits. For higher speed and better density, the resistors used in RTL were replaced by diodes resulting indiode–transistor logic (DTL).Transistor–transistor logic (TTL) then supplanted DTL.
CMOS diagram of aNOT gate, also known as an inverter.MOSFETs are the most common way to make logic gates.
As integrated circuits became more complex, bipolar transistors were replaced with smallerfield-effect transistors (MOSFETs); seePMOS andNMOS. To reduce power consumption still further, most contemporary chip implementations of digital systems now useCMOS logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation.
Other types of logic gates include, but are not limited to:[25]
Uses transistors switching between saturated and cutoff states to perform logic. The transistors require carefully controlled parameters. Economical because few other components are needed, but tends to be susceptible to noise because of the lower voltage levels employed. Often considered to be the father to modern TTL logic.
UsesMOSFETs (metal–oxide–semiconductor field-effect transistors), the basis for most modern logic gates. The MOS logic family includesPMOS logic,NMOS logic,complementary MOS (CMOS), andBiCMOS (bipolar CMOS).
Uses transistors to perform logic but biasing is from constant current sources to prevent saturation and allow extremely fast switching. Has high noise immunity despite fairly low logic levels.
Uses tunnelable q-bits for synthesizing the binary logic bits. The electrostatic repulsive force in between two electrons in the quantum dots assigns the electron configurations (that defines state 1 or state 0) under the suitably driven polarizations. This is a transistorless, currentless, junctionless binary logic synthesis technique allowing it to have very fast operation speeds.
Ferroelectric FET
FeFET
FeFET transistors can retain their state to speed recovery in case of a power loss.[26]
A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used onbuses of theCPU to allow multiple chips to send data. A group of three states driving a line with a suitable control circuit is basically equivalent to amultiplexer, which may be physically distributed over separate devices or plug-in cards.
In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit.
Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as theHarvard Mark I, were built fromrelay logic gates, using electro-mechanicalrelays. Logic gates can be made usingpneumatic devices, such as the Sorteberg relay or mechanical logic gates, including on a molecular scale.[27] Various types of fundamental logic gates have been constructed using molecules (molecular logic gates), which are based on chemical inputs and spectroscopic outputs.[28] Logic gates have been made out ofDNA (seeDNA nanotechnology)[29] and used to create a computer called MAYA (seeMAYA-II). Logic gates can be made fromquantum mechanical effects, seequantum logic gate.Photonic logic gates usenonlinear optical effects.
In principle any method that leads to a gate that isfunctionally complete (for example, either a NOR or a NAND gate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is not needed, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NAND gates, NOR gates, or AND and OR gates).
^Perkins, Franklin (2004)."Exchange with China".Leibniz and China: A Commerce of Light.Cambridge University Press. p. 117.ISBN9780521830249.... one of the traditional orderings of the hexagrams, thexiantian tu ordering made by Shao Yong, was, with a few modifications, the same order found in Leibniz's binary arithmetic.
^Luisa Bonolis; Walther Bothe and Bruno Rossi: The birth and development of coincidence methods in cosmic-ray physics. Am. J. Phys. 1 November 2011; 79 (11): 1133–1150.
