This list isincomplete; you can help byadding missing items.(December 2020)

The following is apartial list ofIntelCPUmicroarchitectures. The list isincomplete, additional details can be found in Intel'stick–tock model,process–architecture–optimization model andTemplate:Intel processor roadmap.

8086

firstx86 processor; initially a temporary substitute for theiAPX 432 to compete withMotorola,Zilog, andNational Semiconductor and to top the successfulZ80. The8088 version, with an 8-bit bus, was used in the originalIBM Personal Computer.

186

included aDMA controller, interrupt controller, timers, andchip select logic. A small number of additional instructions. The80188 was a version with an 8-bit bus.

286

firstx86 processor withprotected mode including segmentation based virtual memory management. Performance improved by a factor of 3 to 4 over 8086. Included instructions relating to protected mode. The80286 had a 24-bit address bus.

i386

first32-bitx86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since. Many additional powerful and valuable new instructions.

i486

Intel's second generation of32-bitx86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining. Faster per MHz than the 386. Small number of new instructions.

P5

original Pentium microprocessors, first x86 processor withsuper-scalar architecture and branch prediction.

P6

used inPentium Pro,Pentium II,Pentium II Xeon,Pentium III, andPentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, RISCμop decode scheme, integrated register renaming andout-of-order execution. Some important new instructions, including conditional moves, which allow the avoidance of costly branch instructions. Added 36-bit physical memory addressing,"Physical Address Extension (PAE)".

• Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to supportmicro-op fusion and smart cache.
• Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in the first Intel Core microprocessors, first x86 to haveshadow register architecture andspeed step technology.

NetBurst

commonly referred to asP7 although its internal name was P68 (P7 was used forItanium). Used inPentium 4,Pentium D, and someXeon microprocessors. Very longpipeline. ThePrescott was a major architectural revision. Later revisions were the first to feature Intel'sx86-64 architecture, enhanced branch prediction and trace cache, and eventually support was added for theNX (No eXecute) bit to implementexecutable-space protection.

Core

reengineered P6-based microarchitecture used inIntel Core 2 andXeon microprocessors, built on a 65 nm process, supportingx86-64 level SSE instruction andmacro-op fusion and enhancedmicro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.

• Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higherFSB and clock speeds,SSE4.1 instructions, support for XOP and F/SAVE and F/STORE instructions, enhanced register alias table and larger integer register file.

Nehalem

released November 17, 2008, built on a 45 nm process and used in theCore i7,Core i5,Core i3 microprocessors. Incorporates the memory controller into the CPU die. Added important powerful new instructions,SSE4.2.

• Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.

Sandy Bridge

32 nm microarchitecture, released January 9, 2011. Formerly called Gesher but renamed in 2007.^[2] First x86 to introduce 256 bitAVX instruction set and implementation of YMM registers.

• Ivy Bridge: successor to Sandy Bridge, using 22 nm process, released in April 2012.

Haswell

22 nm microarchitecture, released June 3, 2013. Added a number of new instructions, includingAVX2 andFMA.

• Broadwell: 14 nm derivative of the Haswell microarchitecture, released in September 2014. Three-cycle FMUL latency, 64 entry scheduler. Formerly called Rockwell.

Skylake

14 nm microarchitecture, released August 5, 2015.

• Kaby Lake: successor to Skylake, released in August 2016, broke Intel'stick-tock schedule due to delays with the 10 nm process.
  • Amber Lake: ultra low power, mobile-only successor to Kaby Lake, using 14+ nm process, released in August 2018 (no architecture changes)^[3]
  • Whiskey Lake: mobile-only successor to Kaby Lake Refresh, using 14++ nm process, released in August 2018 (has hardware mitigations for some vulnerabilities)^[3]
• Skylake-X: high-end desktop, workstation and server microarchitecture, released on June 19, 2017 (HEDT), July 11, 2017 (SP) and August 29, 2017 (W). Introduces support forAVX-512 instruction set.
• Coffee Lake: successor to Kaby Lake, using 14++ nm process, released in October 2017
• Cascade Lake: server and high-end desktop successor toKaby Lake-X andSkylake-X, using 14++ nm process, released in April 2019
• Comet Lake: successor to Coffee Lake, using 14++ nm process, released in August 2019^[4]
• Cooper Lake: server-only, optimized forAI oriented workloads usingbfloat16, with limited availability only to Intel priority partners, using 14++ nm process, released in 2020^[5][6]

Palm Cove

Originally meant to be successor to Skylake, but cancelled after releasing just one chip. Includes theAVX-512 instruction set.^[7][8]

• Cannon Lake: mobile-only successor of Kaby Lake, using Intel's 10 nm process, first and only microarchitecture to implement the Palm Cove core, released in May 2018. Formerly called Skymont, discontinued in December 2019.^[9]

Starting with Cannon Lake, Intel has changed their microarchitecture naming scheme, decoupling core codenames from CPU codenames.^[10]

Sunny Cove

Successor to the Palm Cove core, first non-Atom core to include hardware acceleration forSHA hashing algorithms.^[11]

• Ice Lake: low power, mobile-only successor to Whiskey Lake, using 10 nm process, released in September 2019
• Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Sunny Cove is used in the singular performance core (P-core) of Lakefield processors.^[12] AVX and more advanced instruction sets are disabled due to the E-core not supporting them.
• Ice Lake-SP: server-only successor to Cascade Lake, using 10 nm process, released in April 2021^[5][13]

Cypress Cove

Backport of Sunny Cove to Intel's 14 nm process

• Rocket Lake: Successor to Comet Lake, using Intel's 14++ nm process, released on March 30, 2021^[14][15][16]

Willow Cove

Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem.^[17]

• Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020

Golden Cove

Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions.^[18]

• Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake; uses Intel 7 process (previously known as 10ESF),^[19] released on November 4, 2021.^[20] Golden Cove is used in P-cores of Alder Lake processors.^[21]
• Sapphire Rapids: server and workstation-only, successor to Ice Lake-SP, manufactured on Intel 7 process,^[19][22] released on January 10, 2023. IntroducesAMX.

Raptor Cove

A refresh of Golden Cove with increased L2 and L3 caches and core clocks.

• Raptor Lake: successor to Alder Lake with increased cache sizes, core clocks and the number of E-cores, released on October 20, 2022. Manufactured using Intel 7 process. Raptor Cove is used in the P-cores while the E-cores are still implemented using Gracemont microarchitecture.
• Emerald Rapids: successor to Sapphire Rapids, server- and workstation-only. Fifth-generationXeon Scalable server processors based on theIntel 7 node.

Bonnell

45 nm, low-power, in-order microarchitecture for use inAtom processors.

• Saltwell: 32 nm shrink of the Bonnell microarchitecture.

Silvermont

22 nm, out-of-order microarchitecture for use in Atom processors, released on May 6, 2013.

• Airmont: 14 nm shrink of the Silvermont microarchitecture.

Goldmont

14 nmAtom microarchitecture iteration after Silvermont but borrows heavily from Skylake processors (e.g., GPU), released in April 2016.^[23][24]

• Goldmont Plus: successor to Goldmont microarchitecture, still based on the 14 nm process, released on December 11, 2017.

Tremont

10 nmAtom microarchitecture iteration after Goldmont Plus.^[25]

• Lakefield: mobile-only, Intel's first hybrid processor, released in June 2020. Tremont is used in efficiency cores (E-cores) of Lakefield processors.^[12]
• Jasper Lake: Celeron and Pentium Silver desktop and mobile processors, released in Q1 2021.
• Elkhart Lake: embedded processors targeted atIoT, released in Q1 2021.

Gracemont

Intel 7 process^[19]Atom microarchitecture iteration after Tremont. First Atom class core with AVX and AVX2 support.

• Alder Lake: hybrid processor, succeeds Rocket Lake and Tiger Lake, released on November 4, 2021. Gracemont is used in E-cores of Alder Lake processors.^[21]
• Raptor Lake: a refresh of Alder Lake, released on October 20, 2022.

Larrabee (cancelled 2010)

multi-core in-orderx86-64 updated version of P5 microarchitecture, with wideSIMD vector units and texture sampling hardware for use in graphics.

Xeon Phi

Merced

original Itanium microarchitecture. Used only in the firstItanium microprocessors.

McKinley

enhanced microarchitecture used in the first two generations of theItanium 2 microprocessor. Madison is the 130 nm version.

Montecito

enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements. The Montvale update added demand-based switching (SpeedStep) and core-levellockstep execution.

Tukwila

enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, an integrated memory controller, QuickPath Interconnect, and other improvements e.g. a more active SoEMT.

Poulson

Itanium processor featuring an all-new microarchitecture.^[26] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution.^[27]

Kittson

the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

This sectionneeds expansion. You can help byadding missing information.(October 2024)

4004/4040

8008

8080/8085

iAPX 432

80960

80860^{[note 1]}

XScale

a microarchitecture implementing theARM architecture instruction set.

Atom roadmap^[58]

Fabri­cation process	Micro­architecture	Release date	Processors/SoCs
			MID, smartphone	Tablet	Laptop	Desktop	Embedded	Server	Communication	CE
45 nm	Bonnell	2008	Silverthorne	—	Diamondville		Tunnel Creek, Stellarton	—		Sodaville
		2010	Lincroft		Pineview					Groveland
32 nm	Saltwell	2011	Medfield (Penwell & Lexington), Clover Trail+ (Cloverview)	Clover Trail (Cloverview)	Cedar Trail (Cedarview)			Centerton & Briarwood		Berryville
22 nm	Silvermont	2013	Merrifield (Tangier),[59] Slayton, Moorefield (Anniedale)[60]	Bay Trail-T (Valleyview)	Bay Trail-M (Valleyview)	Bay Trail-D (Valleyview)	Bay Trail-I (Valleyview)	Avoton	Rangeley
014 nm[58]	Airmont	2014	Binghamton & Riverton	Cherry Trail-T (Cherryview)[61]	Braswell[62]			DenvertonCancelled
	Goldmont [63]	2016	BroxtonCancelled	Willow TrailCancelled Apollo Lake	Apollo Lake[64]			Denverton[65]
	Goldmont Plus[66]	2017			Gemini Lake[67] Gemini Lake Refresh[68]
10 nm	Tremont[25]	2020		Lakefield (hybrid)	Lakefield (hybrid)[69] Elkhart Lake[70] Jasper Lake[71]			Jacobsville Parker Ridge[72] Snow Ridge[73]
Intel 7	Gracemont[74]	2021			Alder Lake (hybrid)[75] Raptor Lake (hybrid) Alder Lake-N[76][77] Twin Lake[78]
Intel 4	Crestmont	2023						Grand Ridge
Intel 4 + TSMC N6					Meteor Lake (hybrid)
Intel 3		2024						Sierra Forest
TSMC N3B	Skymont				Lunar Lake (hybrid)
					Arrow Lake (hybrid)
Intel 18A	Darkmont	2026			Panther Lake (hybrid)			Clearwater Forest
	Arctic Wolf				Nova Lake (hybrid)

• List of Intel processors - Consumer Computer or non-consumer workstation
• List of AMD CPU microarchitectures
• Marvell Technology Group XScale microarchitecture
• Transient execution CPU vulnerability

• Intel Automated Relational Knowledgebase

• Intel microprocessors
• Lists of microprocessors
• Intel microarchitectures

• CS1 German-language sources (de)
• Articles with short description
• Short description is different from Wikidata
• Incomplete lists from December 2020
• Articles to be expanded from October 2024
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