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Interrupt request

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(Redirected fromInterrupt request (PC architecture))
Hardware signal sent to a processor to interrupt a running program and handle input
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Diagram about the course of an interrupt routine

In acomputer, aninterrupt request (orIRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special program, aninterrupt handler, to run instead. Hardware interrupts are used to handle events such as receiving data from amodem ornetwork card, key presses, or mouse movements.

Interrupt lines are often identified by an index with the format ofIRQ followed by a number. For example, on theIntel 8259 family ofprogrammable interrupt controllers (PICs) there are eight interrupt inputs commonly referred to asIRQ0 throughIRQ7. Inx86 basedcomputer systems that use two of thesePICs, the combined set of lines are referred to asIRQ0 throughIRQ15. Technically these lines are namedIR0 throughIR7, and the lines on theISA bus to which they were historically attached are namedIRQ0 throughIRQ15 (although historically as the number of hardware devices increased, the total possible number of interrupts was increased by means of cascading requests, by making one of the IRQ numbers cascade to another set or sets of numbered IRQs, handled by one or more subsequent controllers).

Newerx86 systems integrate anAdvanced Programmable Interrupt Controller (APIC) that conforms to the Intel APIC Architecture. Each Local APIC typically support up to 255 IRQ lines, with each I/O APIC typically support up to 24 IRQ lines.[1]

During the early years of personal computing, IRQ management was often of user concern. With the introduction ofplug and play devices this has been alleviated through automatic configuration.[2]

Overview

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When working with personal computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the systemBIOS and recognized by the operating system. These default settings can be altered by advanced users. Modernplug and play technology has not only reduced the need for concern for these settings, but has also virtually eliminated manual configuration.

x86 IRQs

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Early PCs using the Intel 8086/8088 processors only had a single PIC, and are therefore limited to eight interrupts. This was expanded to two PICs with the introduction of the 286 based PCs.

Typically, on systems using theIntel 8259 PIC, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware.

On APIC withIOAPIC systems, typically there are 24 IRQs available, and the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured PCI interrupts and statically configured ISA interrupts. On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers, PCI interrupt lines were routed to the 16 IRQs using a PIR (PCI interrupt routing) table integrated into the BIOS. Operating systems such asWindows 95 OSR2 may use PIR table to process PCI IRQ steering;[3][4] later, the PIR table has been superseded by theACPI _PRT (PCI routing table) protocol. On APIC withMSI systems, typically there are 224 interrupts available.[5]

The easiest way of viewing this information onWindows is to useDevice Manager orSystem Information (msinfo32.exe). OnLinux, IRQ mappings can be viewed by executingcat /proc/interrupts or using theprocinfo utility.

Master PIC

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  • IRQ 0 –system timer (cannot be changed)
  • IRQ 1 –keyboard onPS/2 port (cannot be changed)
  • IRQ 2 –8259 interrupt controller; cascaded signals from IRQs 8–15
  • IRQ 3 –serial portcontroller forserial port 2 (shared with serial port 4, if present)
  • IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present)
  • IRQ 5 –parallel port 3 orISA sound card
  • IRQ 6 –floppy disk controller
  • IRQ 7 – parallel port 1 (shared with parallel port 2, if present). It can also be potentially be shared with a secondary ISA sound card with careful management of the port.

Slave PIC

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Conflicts

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In early IBM-compatiblepersonal computers, anIRQ conflict is a once common hardware error, received when two devices were trying to use the same interrupt request (or IRQ) to signal an interrupt to theProgrammable Interrupt Controller (PIC). The PIC expects interrupt requests from only one device per line, thus more than one device sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze acomputer.

For example, if amodemexpansion card is added into a system and assigned to IRQ4, which is traditionally assigned to theserial port 1, it will likely cause an IRQ conflict. Initially, IRQ 7 was a common choice for the use of asound card, but later IRQ 5 was used when it was found that IRQ 7 would interfere with theprinter port (LPT1). Theserial ports are frequently disabled to free an IRQ line for another device. IRQ 2/9 is the traditional interrupt line for an MPU-401 MIDI port, but this conflicts with theACPI system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets);[6] this means ISAMPU-401 cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled.

In some conditions, twoISA devices could share the same IRQ as long as they were not used simultaneously. To solve this problem, the laterPCI bus allows for IRQ sharing.PCI Express does not have physical interrupt lines, and usesMessage Signaled Interrupts (MSI) to theoperating systems if available.

See also

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References

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  1. ^"IOAPIC - OSDev Wiki".wiki.osdev.org. Retrieved2024-11-07.
  2. ^"IRQ". RetrievedSeptember 13, 2019.
  3. ^"1.3.1.2. PCI Bus IRQ Steering - PC Hardware in a Nutshell, 3rd Edition [Book]".
  4. ^"Plug-and-Play-HOWTO: PCI Interrupts".
  5. ^Coleman, James (2009). "Results, Workstation Class Platform".Reducing Interrupt Latency Through the Use of Message Signalled Interrupts(PDF). Intel Corporation. p. 19.
  6. ^abOshins, Jake (December 30, 2001)."RE: ACPI Machines and IRQ 9 [was: Communicating with the NT developers]". RetrievedApril 17, 2014.

Further reading

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External links

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