 Closed and open Intel 8080 processor | |
| General information | |
|---|---|
| Launched | April 1974; 51 years ago (1974-04) |
| Discontinued | 1990; 35 years ago (1990)[1] |
| Marketed by | Intel |
| Designed by | Intel |
| Common manufacturer |
|
| Performance | |
| Max.CPUclock rate | 2 MHz to 3.125 MHz |
| Data width | 8 bits |
| Address width | 16 bits |
| Architecture and classification | |
| Technology node | 6 μm |
| Instruction set | 8080 |
| Physical specifications | |
| Transistors |
|
| Cores |
|
| Package |
|
| Socket | |
| History | |
| Predecessor | Intel 8008 |
| Successor | Intel 8085 |
| Support status | |
| Unsupported | |
TheIntel 8080 isIntel's second8-bit microprocessor. Introduced in April 1974, the 8080 was an enhanced non-binary compatible successor to the earlierIntel 8008 microprocessor.[3] Originally intended for use inembedded systems such ascalculators,cash registers,computer terminals, andindustrial robots,[4] its performance soon led to adoption in a broader range of systems, ultimately launching themicrocomputer industry.
Several key design choices contributed to the 8080’s success. Its 40‑pin package simplified interfacing compared to the 8008’s 18‑pin design, enabling a more efficientdata bus. The transition toNMOS technology provided faster transistor speeds than the 8008'sPMOS, also making itTTL compatible. An expandedinstruction set and a full16-bit address bus allowed the 8080 to access up to 64 KB of memory, quadrupling the capacity of its predecessor. A broader selection of support chips further enhanced its functionality. Many of these improvements stemmed from customer feedback, as designerFederico Faggin and others at Intel heard from industry about shortcomings in the 8008 architecture.
The 8080 found its way into earlypersonal computers such as theAltair 8800 and subsequentS-100 bus systems, and it served as the original target CPU for theCP/M operating system. It directly influenced the laterx86 architecture which was designed so that itsassembly language closely resembled that of the 8080, permitting many instructions to map directly from one to the other.[5]
Originally operating at aclock rate of 2 MHz, with common instructions taking between 4 and 11 clock cycles, the 8080 was capable of executing several hundred thousandinstructions per second. Later, two faster variants, the 8080A-1 and 8080A-2, offered improved clock speeds of 3.125 MHz and 2.63 MHz, respectively.[6] In most applications, the processor was paired with two support chips, the 8224 clock generator/driver and the 8228 bus controller, to manage its timing and data flow.
Microprocessor customers were reluctant to adopt the 8008 because of limitations such as the single addressing mode, low clock speed, low pin count, and small on-chip stack, which restricted the scale and complexity of software. There were several proposed designs for the 8080, ranging from simply adding stack instructions to the 8008 to a complete departure from all previous Intel architectures.[7] The final design was a compromise between the proposals.
The conception of the 8080 began in the summer of 1971, whenIntel wrapped up development of the4004 and were still working on the8008. After rumors about the "CPU on a chip" came out, Intel started to see interest in the microprocessor from all sorts of customers. At the same time,Federico Faggin – who led the design of the 4004 and became the primary architect of the 8080 – was giving some technical seminars on both of the aforementioned microprocessors and visiting customers. He found that they were complaining about the architecture and performance of said microprocessors, especially the 8008 – as its speed at 0.5 MHz was "not adequate."[7]
Faggin later proposed the chip to Intel's management and pushed for its implementation in the spring of 1972, as development of the 8008 was wrapping up. However, much to his surprise and frustration, Intel didn't approve the project. Faggin says that Intel wanted to see how the market would react to the 4004 and 8008 first, while others noted the problems Intel was having getting its latest generation of memory chips out the door and wanted to focus on that. As a result, Intel didn't approve of the project until fall of that year.[7] Faggin hiredMasatoshi Shima, who helped design the logic of the 4004 with him, from Japan in November 1972. Shima did the detailed design under Faggin's direction,[8] using the design methodology for random logic with silicon gate that Faggin had created for the 4000 family and the 8008.
The 8080 was explicitly designed to be a general-purpose microprocessor for a larger number of customers. Much of the development effort was spent trying to integrate the functionalities of the 8008's supplemental chips into one package. It was decided early in development that the 8080 was not to be binary-compatible with the 8008, instead opting for source compatibility once run through a transpiler, to allow new software to not be subject to the same restrictions as the 8008. For the same reason, as well as to expand the capabilities of stack-based routines and interrupts, the stack was moved to external memory.
Noting the specialized use of general-purpose registers by programmers in mainframe systems, Faggin with Shima andStanley Mazor decided the 8080's registers would be specialized, with register pairs having a different set of uses.[9] This also allowed the engineers to more effectively use transistors for other purposes.
Shima finished the layout in August 1973. Production of the chip later began in December of that year.[7] After the development ofNMOS logic fabrication, a prototype of the 8080 was completed in January 1974. It had a flaw, in that driving with standard TTL devices increased the ground voltage because high current flowed into the narrow line. Intel had already produced 40,000 units of the 8080 at the direction of the sales section before Shima characterized the prototype. After working out some typical last-minute issues, Intel introduced the product in March 1974.[7] It was released a month later as requiring Low-power Schottky TTL (LS TTL) devices. The 8080A fixed this flaw.[10]
Intel offered aninstruction set simulator for the 8080 named INTERP/80 to run compiledPL/M programs. It was written inFORTRAN IV byGary Kildall while he worked as a consultant for Intel.[11][12]
There is only one patent on the 8080 with the following names: Federico Faggin, Masatoshi Shima, Stanley Mazor.
| 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | (bit position) |
| Main registers | ||||||||||||||||
| A | Flags | ProgramStatusWord | ||||||||||||||
| B | C | B | ||||||||||||||
| D | E | D | ||||||||||||||
| H | L | H (indirect address) | ||||||||||||||
| Index registers | ||||||||||||||||
| SP | StackPointer | |||||||||||||||
| Program counter | ||||||||||||||||
| PC | ProgramCounter | |||||||||||||||
| Status register | ||||||||||||||||
| S | Z | 0 | AC | 0 | P | 1 | C | Flags[13] | ||||||||
The Intel 8080 is the successor to the8008. It uses the same basicinstruction set andregister model as the 8008, although it is neithersource code compatible norbinary code compatible with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. Whereas the 8008 required the use of the HL register pair to indirectly access its 14-bit memory space, the 8080 has addressing modes to directly access its full 16-bit memory space. The internal 7-level push-downcall stack of the 8008 was replaced by a dedicated 16-bit stack-pointer (SP) register. The 8080's 40-pinDIP packaging provides a 16-bitaddress bus and an 8-bitdata bus which more efficiently access 64 KiB (216 bytes) of memory.
The processor has seven 8-bitregisters (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL, referred to as B, D and H in Intel documents) depending on the particular instruction. Some instructions can also use the HL register pair as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereferenced memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bitstack pointer to memory, replacing the 8008's internalstack, and a 16-bitprogram counter.
The processor maintains internalflag bits (astatus register), which indicate the results of arithmetic and logical instructions. Only certain instructions affect the flags. The flags are:
The carry bit can be set or complemented by specific instructions. Conditional-branch instructions test the various flag status bits. The accumulator and the flags together are called the PSW, or program status word. PSW can be pushed to or popped from the stack.
As with many other 8-bit processors, all instructions are encoded in one byte (including register numbers, but excluding immediate data), for simplicity. Some can be followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. Like more advanced processors, it has automatic CALL and RET instructions for multi-level procedure calls and returns (which can even be conditionally executed, like jumps) and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke a correspondinginterrupt service routine, but are also often employed as fastsystem calls. The slowest instruction isXTHL, which exchanges the register pair HL with the last item pushed on the stack.
All 8-bit operations with two operands can only be performed on the 8-bitaccumulator (the A register). The other operand can be either an immediate value, another 8-bit register, or a memory byte addressed by the 16-bit register pair HL. Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte. Due to the regular encoding of theMOV instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself (MOV B,B, for instance), which are of little use, except for delays. However, the systematic opcode forMOV M,M is instead used to encode the halt (HLT) instruction, halting execution until an external reset or interrupt occurs.
Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL, referred to as B, D, H in Intel documents) or SP can be loaded with an immediate 16-bit value (usingLXI), incremented or decremented (usingINX andDCX), or added to HL (usingDAD). By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction. The only 16-bit instructions that affect any flag isDAD, which sets the CY (carry) flag in order to allow for programmed 24-bit or 32-bitarithmetic (or larger), needed to implementfloating-point arithmetic. BC, DE, HL, or PSW can be copied to and from the stack usingPUSH andPOP. A stack frame can be allocated usingDAD SP andSPHL. A branch to a computed pointer can be executed withPCHL.LHLD loads HL from directly addressed memory andSHLD stores HL likewise. TheXCHG[14] instruction exchanges the values of the HL and DE register pairs.XTHLexchanges last item pushed on stack with HL. None of these 16-bit operations were supported on the earlier Intel 8008.
| Opcode | Operands | Mnemonic | Clocks | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | — | NOP | 4 | No operation |
| 0 | 0 | RP | 0 | 0 | 0 | 1 | datlo | dathi | LXIrp,data | 10 | RP ←data | |
| 0 | 0 | RP | 0 | 0 | 1 | 0 | — | — | STAXrp | 7 | (RP) ← A [BC or DE only] | |
| 0 | 0 | RP | 0 | 0 | 1 | 1 | — | — | INXrp | 5 | RP ← RP + 1 | |
| 0 | 0 | DDD | 1 | 0 | 0 | — | — | INRddd | 5/10 | DDD ← DDD + 1 | ||
| 0 | 0 | DDD | 1 | 0 | 1 | — | — | DCRddd | 5/10 | DDD ← DDD - 1 | ||
| 0 | 0 | DDD | 1 | 1 | 0 | data | — | MVIddd,data | 7/10 | DDD ← data | ||
| 0 | 0 | RP | 1 | 0 | 0 | 1 | — | — | DADrp | 10 | HL ← HL + RP | |
| 0 | 0 | RP | 1 | 0 | 1 | 0 | — | — | LDAXrp | 7 | A ← (RP) [BC or DE only] | |
| 0 | 0 | RP | 1 | 0 | 1 | 1 | — | — | DCXrp | 5 | RP ← RP - 1 | |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | — | RLC | 4 | A1-7 ← A0-6; A0 ← Cy ← A7 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | RRC | 4 | A0-6 ← A1-7; A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | — | RAL | 4 | A1-7 ← A0-6; Cy ← A7; A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | — | — | RAR | 4 | A0-6 ← A1-7; Cy ← A0; A7 ← Cy |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | addlo | addhi | SHLDadd | 16 | (add) ← HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | — | DAA | 4 | If A0-3 > 9 OR AC = 1 then A ← A + 6; then if A4-7 > 9 OR Cy = 1 then A ← A + 0x60 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | addlo | addhi | LHLDadd | 16 | HL ← (add) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | — | — | CMA | 4 | A ← ¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | addlo | addhi | STAadd | 13 | (add) ← A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | — | STC | 4 | Cy ← 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | addlo | addhi | LDAadd | 13 | A ← (add) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | CMC | 4 | Cy ← ¬Cy |
| 0 | 1 | DDD | SSS | — | — | MOVddd,sss | 5/7 | DDD ← SSS | ||||
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | — | — | HLT | 7 | Halt |
| 1 | 0 | ALU | SSS | — | — | ADD ADC SUB SBB ANA XRA ORA CMPsss | 4/7 | A ← A [ALU operation] SSS | ||||
| 1 | 1 | CC | 0 | 0 | 0 | — | — | Rcc (RET conditional) | 5/11 | If cc true, PC ← (SP), SP ← SP + 2 | ||
| 1 | 1 | RP | 0 | 0 | 0 | 1 | — | — | POPrp | 10 | RP ← (SP), SP ← SP + 2 | |
| 1 | 1 | CC | 0 | 1 | 0 | addlo | addhi | Jccadd (JMP conditional) | 10 | If cc true, PC ← add | ||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | addlo | addhi | JMPadd | 10 | PC ← add |
| 1 | 1 | CC | 1 | 0 | 0 | addlo | addhi | Cccadd (CALL conditional) | 11/17 | If cc true, SP ← SP - 2, (SP) ← PC, PC ← add | ||
| 1 | 1 | RP | 0 | 1 | 0 | 1 | — | — | PUSHrp | 11 | SP ← SP - 2, (SP) ← RP | |
| 1 | 1 | ALU | 1 | 1 | 0 | data | — | ADI ACI SUI SBI ANI XRI ORI CPIdata | 7 | A ← A [ALU operation] data | ||
| 1 | 1 | N | 1 | 1 | 1 | — | — | RSTn | 11 | SP ← SP - 2, (SP) ← PC, PC ← N x 8 | ||
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | — | — | RET | 10 | PC ← (SP), SP ← SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | addlo | addhi | CALLadd | 17 | SP ← SP - 2, (SP) ← PC, PC ← add |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | port | — | OUTport | 10 | Port ← A |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | port | — | INport | 10 | A ← Port |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | — | XTHL | 18 | HL ↔ (SP) |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | — | — | PCHL | 5 | PC ← HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | — | — | XCHG | 4 | HL ↔ DE |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | — | — | DI | 4 | Disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | — | SPHL | 5 | SP ← HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | — | EI | 4 | Enable interrupts |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | Clocks | Description |
| SSS DDD | 2 | 1 | 0 | CC | ALU | RP | ||||||
| B | 0 | 0 | 0 | NZ | ADD ADI (A ← A + arg) | BC | ||||||
| C | 0 | 0 | 1 | Z | ADC ACI (A ← A + arg + Cy) | DE | ||||||
| D | 0 | 1 | 0 | NC | SUB SUI (A ← A - arg) | HL | ||||||
| E | 0 | 1 | 1 | C | SBB SBI (A ← A - arg - Cy) | SP or PSW | ||||||
| H | 1 | 0 | 0 | PO | ANA ANI (A ← A ∧ arg) | |||||||
| L | 1 | 0 | 1 | PE | XRA XRI (A ← A ⊻ arg) | |||||||
| M | 1 | 1 | 0 | P | ORA ORI (A ← A ∨ arg) | |||||||
| A | 1 | 1 | 1 | N | CMP CPI (A - arg) | |||||||
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
The 8080 supports 256input/output (I/O) ports,[15] accessed via dedicated I/O instructions taking port addresses as operands.[16] This I/O mapping scheme is regarded as an advantage, as it frees up the processor's limited address space. Many CPU architectures instead use so-calledmemory-mapped I/O (MMIO), in which a common address space is used for both RAM and peripheral chips. This removes the need for dedicated I/O instructions, although a drawback in such designs may be that special hardware must be used to insert wait states, as peripherals are often slower than memory. However, in some simple 8080 computers, I/O is indeed addressed as if they were memory cells, "memory-mapped", leaving the I/O commands unused. I/O addressing can also sometimes employ the fact that the processor outputs the same 8-bit port address to both the lower and the higher address byte (i.e.,IN 05h would put the address 0505h on the 16-bit address bus). Similar I/O-port schemes are used in the backward-compatible Zilog Z80 and Intel 8085, and the closely related x86 microprocessor families.
One of the bits in the processor state word (see below) indicates that the processor is accessing data from the stack. Using this signal, it is possible to implement a separate stack memory space. This feature is seldom used.
For more advanced systems, during the beginning of each machine cycle, the processor places an eight bit status word on the data bus. This byte contains flags that determine whether the memory or I/O port is accessed and whether it is necessary to handle an interrupt.
The interrupt system state (enabled or disabled) is also output on a separate pin. For simple systems, where the interrupts are not used, it is possible to find cases where this pin is used as an additional single-bit output port (the popularRadio-86RK computer made in theSoviet Union, for instance).
Hardwareinterrupts are initiated by asserting the interrupt request (INT) pin. At the next opcode fetch cycle (M1), the interrupt will be acknowledged with the INTA state code. At this time, an instruction is "jammed" (Intel's word) by external hardware on the data bus. This can be a one-byteRST instruction, or if using anIntel 8259, aCALL instruction. Interrupts may be enabled and disabled withEI andDI instructions, respectively. Interrupts are disabled after an INTA; they must be re-enabled explicitly by theinterrupt service routine. The 8080 does not supportnon-maskable interrupts.
The following 8080/8085assembler source code is for a subroutine namedmemcpy that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations.
100010001000 1A1001 771002 131003 231004 0B1005 781006 B11007 C2 00 10100A C9 | ; memcpy --; Copy a block of memory from one location to another.;; Entry registers; BC - Number of bytes to copy; DE - Address of source data block; HL - Address of target data block;; Return registers; BC - Zeroorg1000h;Origin at 1000hmemcpypublicloop:ldaxd;Load A from the address pointed by DEmovm,a;Store A into the address pointed by HLinxd;Increment DEinxh;Increment HLdcxb;Decrement BC (does not affect Flags)mova,b;Copy B to A (so as to compare BC with zero)orac;A = A | C (are both B and C zero?)jnzloop;Jump to 'loop:' if the zero-flag is not set.ret;Return |
The address bus has its own 16 pins, and the data bus has 8 pins that are usable without any multiplexing. Using the two additional pins (read and write signals), it is possible to assemble simple microprocessor devices very easily. Only the separate IO space, interrupts, and DMA need added chips to decode the processor pin signals. However, the pin load capacity is limited; even simple computers often require bus amplifiers.
The processor needs three power sources (−5, +5, and +12 V) and two non-overlapping high-amplitude synchronizing signals. However, at least the late Soviet version КР580ВМ80А was able to work with a single +5 V power source, the +12 V pin being connected to +5 V and the −5 V pin to ground.
The pin-out table, from the chip's accompanying documentation, describes the pins as follows:
| Pin number | Signal | Type | Comment |
|---|---|---|---|
| 1 | A10 | Output | Address bus 10 |
| 2 | GND | — | Ground |
| 3 | D4 | Bidirectional | Bidirectional data bus. The processor also momentarily transmits the "processor state" during SYNC^φ1, providing information about what the processor is currently doing:
|
| 4 | D5 | ||
| 5 | D6 | ||
| 6 | D7 | ||
| 7 | D3 | ||
| 8 | D2 | ||
| 9 | D1 | ||
| 10 | D0 | ||
| 11 | −5 V | — | The −5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged. |
| 12 | RESET | Input | Reset. This active low signal forces execution of commands located at address 0000. The content of other processor registers is not modified. |
| 13 | HOLD | Input | Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state. |
| 14 | INT | Input | Interrupt request |
| 15 | φ2 | Input | The second phase of the clock generator signal |
| 16 | INTE | Output | The processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. However, in simple computers it was sometimes used as a single bit output port for various purposes. |
| 17 | DBIN | Output | Read (the processor reads from memory or input port) |
| 18 | WR- | Output | Write (the processor writes to memory or output port). This is an active low output. |
| 19 | SYNC | Output | Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g.,8238Archived September 18, 2023, at theWayback Machine-System Controller and Bus Driver. |
| 20 | +5 V | — | The + 5 V power supply |
| 21 | HLDA | Output | Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus |
| 22 | φ1 | Input | The first phase of the clock generator signal |
| 23 | READY | Input | Wait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode. |
| 24 | WAIT | Output | Wait (indicates that the processor is in the waiting state) |
| 25 | A0 | Output | Address bus |
| 26 | A1 | ||
| 27 | A2 | ||
| 28 | 12 V | — | The +12 V power supply. This must be thelast connected and first disconnected power source. |
| 29 | A3 | Output | The address bus; can switch into high impedance state on demand |
| 30 | A4 | ||
| 31 | A5 | ||
| 32 | A6 | ||
| 33 | A7 | ||
| 34 | A8 | ||
| 35 | A9 | ||
| 36 | A15 | ||
| 37 | A12 | ||
| 38 | A13 | ||
| 39 | A14 | ||
| 40 | A11 |
A key factor in the success of the 8080 was the broad range of support chips available, providing serial communications, counter/timing, input/output, direct memory access, and programmable interrupt control amongst other functions:
The 8080integrated circuit has anNMOS design, which employed non‑saturatedenhancement mode transistors as loads,[18][19] which demanded supplementary voltage levels (+12 V and −5 V) alongside the standardTTL compatible +5 V.
It was manufactured in asilicon gate process using a minimal feature size of 6 μm. A single layer of metal is used tointerconnect the approximately 4,500 transistors[20] in the design, but the higherresistancepolysilicon layer, which required higher voltage for some interconnects, is implemented with transistor gates. Thedie size is approximately 20 mm2.
The 8080 was used in many early microcomputers, such as the MITSAltair 8800 Computer,Processor TechnologySOL-20 Terminal Computer andIMSAI 8080 Microcomputer, forming the basis for machines running theCP/M operating system (the later, almost fully compatible and more able,Zilog Z80 processor would capitalize on this, with Z80 and CP/M becoming the dominant CPU and OS combination of the periodc. 1976 to 1983 much likex86 andMS-DOS a decade later).
In 1979, even after the introduction of the Z80 and 8085 processors, five manufacturers of the 8080 were selling an estimated 500,000 units per month at a price around $3 to $4 each.[21]
The firstsingle-board microcomputers, such asMYCRO-1 and thedyna-micro / MMD-1 (see:Single-board computer) were based on the Intel 8080. One of the early uses of the 8080 was made in the late 1970s by Cubic-Western Data of San Diego, California, in its Automated Fare Collection Systems custom designed for mass transit systems around the world. An early industrial use of the 8080 is as the "brain" of the DatagraphiX Auto-COM (Computer Output Microfiche) line of products which takes large amounts of user data from reel-to-reel tape and images it onto microfiche. The Auto-COM instruments also include an entire automated film cutting, processing, washing, and drying sub-system.
Several earlyarcade video games were built around the 8080 microprocessor. The first commercially available arcade video game to incorporate a microprocessor wasGun Fight,Midway Games' 8080-based reimplementation ofTaito's discrete-logicWestern Gun, which was released in November 1975.[22][23][24][25] (A pinball machine which incorporated aMotorola6800 processor,The Spirit of '76, had already been released the previous month.[26][27]) The 8080 was then used in later Midway arcade video games[28] and in Taito's 1978Space Invaders, one of the most successful and well-known of all arcade video games.[29][30]
Zilog introduced theZ80, which has a compatiblemachine language instruction set and initially used the same assembly language as the 8080, but for legal reasons, Zilog developed a syntactically-different (but code compatible) alternativeassembly language for the Z80. At Intel, the 8080 was followed by the compatible and electrically more elegant8085.
Later, Intel issued the assembly-language compatible (but not binary-compatible) 16-bit8086 and then the 8/16-bit8088, which was selected byIBM for its newPC to be launched in 1981. LaterNEC made theNEC V20 (an 8088 clone withIntel 80186 instruction set compatibility) which also supports an 8080 emulation mode. This is also supported by NEC'sV30 (a similarly enhanced 8086 clone). Thus, the 8080, via itsinstruction set architecture (ISA), made a lasting impact on computer history.
A number of processors compatible with the Intel 8080A were manufactured in theEastern Bloc: theKR580VM80A (initially marked as КР580ИК80) in theSoviet Union, the MCY7880[31] made by Unitra CEMI inPoland, the MHB8080A[32] made byTESLA inCzechoslovakia, the 8080APC[32] made byTungsram / MEV inHungary, and the MMN8080[32] made byMicroelectronica Bucharest inRomania.
As of 2017[update], the 8080 is still in production at Lansdale Semiconductors.[33]
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The 8080 also changed how computers were created. When the 8080 was introduced, computer systems were usually created by computer manufacturers such asDigital Equipment Corporation,Hewlett-Packard, orIBM. A manufacturer would produce the whole computer, including processor, terminals, and system software such as compilers and operating system. The 8080 was designed for almost any applicationexcept a complete computer system. Hewlett-Packard developed theHP 2640 series of smart terminals around the 8080. TheHP 2647 is a terminal which runs the programming languageBASIC on the 8080.Microsoft's founding product,Microsoft BASIC, was originally programmed for the 8080.
The 8080 and8085 gave rise to the 8086, which was designed as asource code compatible, albeit notbinary compatible, extension of the 8080.[34] This design, in turn, later spawned thex86 family of chips, which continue to be Intel's primary line of processors. Many of the 8080's core machine instructions and concepts survive in the widespread x86 platform. Examples include the registers namedA,B,C, andD and many of the flags used to control conditional jumps. 8080 assembly code can still be directly translated into x86 instructions,[vague] since all of its core elements are still present.
US patent 4010449, Federico Faggin,Masatoshi Shima, Stanley Mazor, "MOS computer employing a plurality of separate chips", issued March 1, 1977 . This patent contains three claims. The first two relate to thestatus word multiplexed onto the data bus. The third claim is for theRST 7 instruction which can be invoked by pulling the data bus high. Theprior art 8008RST 7 required more complicated instruction jamming circuitry.
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