 An Intel C8008-1 processor variant with purple ceramic, gold-plated metal lid and pins | |
| General information | |
|---|---|
| Launched | April 1972 |
| Discontinued | 1983[1] |
| Marketed by | Intel |
| Designed by | Computer Terminal Corporation (CTC) |
| Common manufacturer |
|
| Performance | |
| Max.CPUclock rate | 500 kHz to 800 kHz |
| Data width | 8 bits |
| Address width | 14 bits |
| Architecture and classification | |
| Application | Computer terminals,calculators, bottling machines, 1970sASEAindustrial robots[2] (IRB 6), simplecomputers, etc. |
| Technology node | 10 μm |
| Instruction set | 8008 |
| Physical specifications | |
| Transistors |
|
| Package |
|
| Socket | |
| History | |
| Successor | Intel 8080 |
| Support status | |
| Unsupported | |
TheIntel 8008 ("eight-thousand-eight" or "eighty-oh-eight") is an early8-bit microprocessor capable of addressing 16 KB of memory, introduced in April 1972. The 8008 architecture was designed byComputer Terminal Corporation (CTC) and was implemented and manufactured byIntel. While the 8008 was originally designed for use in CTC'sDatapoint 2200 programmable terminal, an agreement between CTC and Intel permitted Intel to market the chip to other customers afterSeiko expressed an interest in using it for acalculator.
In order to address several issues with theDatapoint 3300, including excessive heat radiation,Computer Terminal Corporation (CTC) designed the architecture of the 3300's planned successor with a CPU as part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, CTC co-founder Austin O. "Gus" Roche turned to Intel, then primarily a vendor of memory chips.[3] Roche met withBob Noyce, who expressed concern with the concept; John Frassanito recalls that:
"Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer."[3]
Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a US$50,000 development contract in early 1970 (equivalent to $405,000 in 2024).Texas Instruments (TI) was also brought in as a second supplier.[citation needed]
In December 1969, Intel engineerStan Mazor and a representative of CTC met to discuss options for the logic chipset to power a new CTC business terminal. Mazor, who had been working withTed Hoff on the development of theIntel 4004, proposed that a one-chip programmable microprocessor might be less cumbersome and ultimately more cost effective than building a custom logic chipset. CTC agreed and development work began on the chip, which at the time was known as the 1201.[4]
TI was able to make samples of the 1201 based on Intel drawings, calling it the TMX 1795. These proved to be buggy and were rejected.[5] Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal usingserial discreteTTL instead of waiting for a single-chip CPU. The new system was released as theDatapoint 2200 in the spring of 1970, with their first sale toGeneral Mills on 25 May 1970.[3] CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Later in early 1971, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler 4004 used by Busicom in their business calculators.[4] A small re-design followed, under the leadership ofFederico Faggin, the designer of the4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.[3]
By that point, CTC had once again moved on, this time to the parallel-architecture Datapoint 2200 II, which was faster than the 1201. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at US$120 (equivalent to $902 in 2024). This renaming tried to ride off the success of the 4004 chip, by presenting the 8008 as simply a 4 to 8 port, but the 8008 isnot based on the4004.[6] The 8008 went on to be a commercially successful design. This was followed by the popularIntel 8080, and then the hugely successfulIntel x86 family.[3]
In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for aDigital Equipment CorporationPDP-11.[7] The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data.
The 8008 was the CPU for the very first commercial non-calculatorpersonal computers (excluding the Datapoint 2200 itself): the USSCELBI kit and the pre-built FrenchMicral N and CanadianMCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's2640 family of computer terminals.[8]
In 1973, Intel offered aninstruction set simulator for the 8008 named INTERP/8.[9] It was written inFORTRAN IV byGary Kildall while he worked as a consultant for Intel.[10][11]
The 8008 architecture includes the following features:[12]
The 8008 was provided in an 18-pindual in-line package.[12]
| 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | (bit position) |
| Main registers | ||||||||||||||
| A | Accumulator | |||||||||||||
| B | B register | |||||||||||||
| C | C register | |||||||||||||
| D | D register | |||||||||||||
| E | E register | |||||||||||||
| H | H register(indirect) | |||||||||||||
| L | L register(indirect) | |||||||||||||
| Program counter | ||||||||||||||
| PC | ProgramCounter | |||||||||||||
| Push-down address call stack | ||||||||||||||
| AS | Call level 1 | |||||||||||||
| AS | Call level 2 | |||||||||||||
| AS | Call level 3 | |||||||||||||
| AS | Call level 4 | |||||||||||||
| AS | Call level 5 | |||||||||||||
| AS | Call level 6 | |||||||||||||
| AS | Call level 7 | |||||||||||||
| Flags | ||||||||||||||
| C | P | Z | S | Flags[13][a] | ||||||||||
The 8008 was implemented in 10 μm silicon-gate enhancement-modePMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.[14]Register–register loads and ALU operations take 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) take 11 T-states (44 μs).[15]The 8008 is a little slower in terms ofinstructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bitIntel 4004 andIntel 4040.[16] but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500transistors.[17]
The chip, limited by its 18-pinDIP, has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory.[18] For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8input ports and 24 output ports.[14]
For controller andCRT terminal use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors.
The subsequent 40-pinNMOSIntel 8080 expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.
TheIntel 8085 is an electrically modernized version of the 8080 that usesdepletion-mode transistors and also added two new instructions.
TheIntel 8086, the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, andZ80, but also in the instruction set of modernx86 processors (although the instruction encodings are different).
Instructions are one to three bytes long. The instruction format is an opcode byte, followed by up to two bytes of operands. Operands can be an address, a constant, a register, or the memory pointed to by the HL register pair, referenced as M. The 8008 has the JMP (jump) instruction which replaces the program counter with a new memory address. Additionally, the CAL (call) and RET (return) instructions provide seven levels of subroutine invocations. The RST (restart) instruction is a one byte shortcut to execute eight subroutines located in the first 64 instruction bytes. The subroutines are located at fixed addresses of 00h, 08h, 10h, ..., 38h. These are intended to be supplied to external hardware in order to invoke interrupt service routines, or they can be employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or immediate value. Results are always deposited to register A. Instructions operate on 8-bits only; there are no 16-bit operations. Increments and decrements are supported for most registers but, curiously, not A. Register A supports four rotate instructions.
All instructions execute in 3 to 11 states. Each state requires two clocks.
| Opcode | Operands | Mnemonic | States | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | X | — | — | HLT | 4 | Halt |
| 0 | 0 | DDD | 0 | 0 | 0 | — | — | INr | 5 | DDD ← DDD + 1 (except A and M) | ||
| 0 | 0 | DDD | 0 | 0 | 1 | — | — | DCr | 5 | DDD ← DDD - 1 (except A and M) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | — | — | RLC | 5 | A1-7 ← A0-6; A0 ← Cy ← A7 |
| 0 | 0 | CC | 0 | 1 | 1 | — | — | Rcc (RET conditional) | 3/5 | If cc true, P ← (stack) | ||
| 0 | 0 | ALU | 1 | 0 | 0 | data | — | ADI ACI SUI SBI NDI XRI ORI CPIdata | 8 | A ← A [ALU operation] data | ||
| 0 | 0 | N | 1 | 0 | 1 | — | — | RSTn | 5 | (stack) ← P, P ← N x 8 | ||
| 0 | 0 | DDD | 1 | 1 | 0 | data | — | LrIdata (Load r with immediate data) | 8/9 | DDD ← data | ||
| 0 | 0 | X | X | X | 1 | 1 | 1 | — | — | RET | 5 | P ← (stack) |
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | — | — | RRC | 5 | A0-6 ← A1-7; A7 ← Cy ← A0 |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | — | — | RAL | 5 | A1-7 ← A0-6; Cy ← A7; A0 ← Cy |
| 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | — | — | RAR | 5 | A0-6 ← A1-7; Cy ← A0; A7 ← Cy |
| 0 | 1 | CC | 0 | 0 | 0 | addlo | addhi | Jccadd (JMP conditional) | 9/11 | If cc true, P ← add | ||
| 0 | 1 | 0 | 0 | port | 1 | — | — | INPport | 8 | A ← Port(0-7) | ||
| 0 | 1 | port | 1 | — | — | OUTport | 6 | Port(8-31) ← A | ||||
| 0 | 1 | CC | 0 | 1 | 0 | addlo | addhi | Cccadd (CAL conditional) | 9/11 | If cc true, (stack) ← P, P ← add | ||
| 0 | 1 | X | X | X | 1 | 0 | 0 | addlo | addhi | JMPadd | 11 | P ← add |
| 0 | 1 | X | X | X | 1 | 1 | 0 | addlo | addhi | CALadd | 11 | (stack) ← P, P ← add |
| 1 | 0 | ALU | SSS | — | — | ADr ACr SUr SBr NDr XRr ORr CPr | 5/8 | A ← A [ALU operation] SSS | ||||
| 1 | 1 | DDD | SSS | — | — | Lds (Load d with s) | 5/7/8 | DDD ← SSS | ||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | HLT | 4 | Halt |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | States | Description |
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
| A | 0 | 0 | 0 | FC, C false | ADr ADI (A ← A + arg) | |||||||
| B | 0 | 0 | 1 | FZ, Z false | ACr ACI (A ← A + arg + Cy) | |||||||
| C | 0 | 1 | 0 | FS, S false | SUr SUI (A ← A - arg) | |||||||
| D | 0 | 1 | 1 | FP, P odd | SBr SBI (A ← A - arg - Cy) | |||||||
| E | 1 | 0 | 0 | TC, C true | NDr NDI (A ← A ∧ arg) | |||||||
| H | 1 | 0 | 1 | TZ, Z true | XRr XRI (A ← A ⊻ arg) | |||||||
| L | 1 | 1 | 0 | TS, S true | ORr ORI (A ← A ∨ arg) | |||||||
| M | 1 | 1 | 1 | TP, P even | CPr CPI (A - arg) | |||||||
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
The following 8008assembly source code is for a subroutine namedMEMCPY that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler.
001700 000 001701 000 001702 000 001703 000 001704 000 001705 000 002000 066 304 002002 056 003 002004 327 002005 060 002006 317 002007 302 002010 261 002011 053 002012 302 002013 024 001 002015 320 002016 301 002017 034 000 002021 310 002022 066 300 002024 056 003 002026 302 002027 207 002030 340 002031 060 002032 301 002033 217 002034 350 002035 364 002036 337 002037 066 302 002041 056 003 002043 302 002044 207 002045 340 002046 060 002047 301 002050 217 002051 350002052 364002053 373 002054 104 007 004002057 | ; MEMCPY --; Copy a block of memory from one location to another.;; Entry parameters; SRC: 14-bit address of source data block; DST: 14-bit address of target data block; CNT: 14-bit count of bytes to copyORG1700Q;Data at 001700qSRCDFB0;SRC, low byteDFB0; high byteDSTDFB0;DST, low byteDFB0; high byteCNTDFB0;CNT, low byteDFB0; high byteORG2000Q;Code at 002000qMEMCPYLLICNTAND255;HL = addr(CNT)LHICNTSHR8;(AND and SHR not supported)LCM;BC = CNTINLLBMLOOPLAC;If BC = 0,ORBRTZ;ReturnDECCNTLAC;BC = BC - 1SUI1LCALABSBI0LBAGETSRCLLISRCAND255;HL = addr(SRC)LHISRCSHR8LAC;HL = SRC + BCADM;E = C + (HL)LEA;(lower sum)INL;point to upper SRCLABACM;H = B + (HL) + CYLHA;(upper sum)LLE;L = ELDM;Load D from (HL)GETDSTLLIDSTAND255;HL = addr(DST)LHIDSTSHR8LAC;HL = DST + BCADM;ADD code same as aboveLEAINLLABACMLHALLELMD;Store D to (HL)JMPLOOP;Repeat the loopEND |
In the code above, all values are given in octal. LocationsSRC,DST, andCNT are 16-bit parameters for the subroutine namedMEMCPY. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored inlittle-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with theCNT parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.
The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file.
002000 307 002001 206 015 004002004 370 002005 206 015 004002010 021 002011 110 000 004002014 007 002015 316002016 364 002017 341 002020 315002021 353 002022 331002023 040002024 013 002025 030 002026 007 002027 | ; MEMCPY2 --; Copy a block of memory from one location to another;; Entry parameters in registers; HL: 14-bit address of source data block; DE: 14-bit address of target data block; C: 8-bit count of bytes to copy. (1 to 256 bytes)ORG2000Q;Code at 002000qMEMCPY2LAM;Read source byte into ACALXCHGI;Exchange HL<->DE and increment DELMA;Save A to target byteCALXCHGI;Exchange HL<->DE and increment DEDCC;Decrement byte counterJFZMEMCPY2;Continue for all bytesRET;Exchange DE and HL register pairs then increment DE as 16 bitsXCHGILBL;Exchange L and ELLELEBLBH;Exchange H and DLHDLDBINE;Inc E, low byte of DERFZ;Return if no carryIND;Otherwise inc high byte DRETEND |
Interrupts on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.
At this point, there is a problem. The 8008 has no provision to save itsarchitectural state. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardwarestack or a pair of read/writeregisters must be attached to the 8008 via the I/O ports to help save the state of the 8008.[19]
First, the 4004 and the 8008 are entirely different chips. Marketing makes them sound like it's just a 4-bit and 8-bit version, but they're totally different.