| General information | |
|---|---|
| Launched | 2017 |
| Designed by | IBM |
| Common manufacturer | |
| Performance | |
| Max.CPUclock rate | 5.2[2] GHz |
| Physical specifications | |
| Cores |
|
| Cache | |
| L1cache | 128 KB instruction 128 KB data per core |
| L2 cache | 2 MB instruction 4 MB data per core |
| L3 cache | 128 MB shared |
| Architecture and classification | |
| Technology node | 14 nm[3] |
| Instruction set | z/Architecture |
| History | |
| Predecessor | z13 |
| Successor | z15 |
Thez14 is amicroprocessor made byIBM for theirz14mainframe computers, announced on July 17, 2017.[2][4] Manufactured atGlobalFoundries'East Fishkill, New York fabrication plant.[1] IBM stated that it is the world's fastest microprocessor byclock rate at 5.2 GHz,[2] with a 10% increased performance per core and 30% for the whole chip compared to its predecessor thez13.[5]
The Processor Unit chip (PU chip) has an area of 696 mm2 (25.3 × 27.5 mm) and consists of 6.1 billiontransistors.[3] It is fabricated using GlobalFoundries'14 nmFinFETsilicon on insulatorfabrication process, using 17 layers of metal and supporting speeds of 5.2 GHz, which is higher than its predecessor, the z13.[3] The PU chip has 10 cores but can have 7–10 cores (or "processor units" in IBM's parlance) enabled depending on configuration. The z14 cores support two-waysimultaneous multithreading for more applications than previously available.
The PU chip is packaged in a single-chip module, which is the same as its predecessor, but a departure from previous designs which were mounted on largemulti-chip modules. A computer drawer consists of six PU chips and one Storage Controller (SC) chip containing the L4 cache.[3]
The cores implement theCISCz/Architecture with asuperscalar,out-of-orderpipeline. z14 has acryptographiccoprocessor, called CPACF, attached to each core, used forrandom number generation,hashing,encryption and decrypting and compression. Further enhancements include an optimization of the core's pipeline, doubling the on-chip caches, betterbranch prediction, a new decimal arithmeticSIMD engine designed to boostCOBOL andPL/I code, a "guarded storage facility" that helpsJava applications duringgarbage collection, and other enhancements that increase the cores' performance compared to the predecessors.[3]
The instruction pipeline has an instruction queue that can fetch 6 instructions per cycle; and issue up to 10 instructions per cycle. Each core has a private 128KB L1 instructioncache, a private 128 KB L1 data cache, a private 2MB L2 instruction cache, and a private 4 MB L2 data cache. In addition, there is a 128 MB shared L3 cache implemented ineDRAM.[3]
The z14 chip has on board multi-channelDDR4 RAMmemory controller supporting aRAID-like configuration to recover from memory faults. The z14 also includes twoGX bus as well as two new Gen 3 PCIe controllers for accessing host channel adapters and peripherals.[3] The PU chips has three X-buses for communications to three neighboring PU chips and the SC chip.
A compute drawer consists of two clusters. Each cluster comprises either two or three PU chips. The two clusters share a single Storage Controller chip (SC chip). Even though each PU chip has 128 MB L3 cache shared by the 10 cores and other on-die facilities, the SC chip adds 672 MB off-dieeDRAML4 cache shared by the six PU chips in the drawer. The SC chips also handle the communications between the sets of three PU in the drawer as well as communications between drawers using the A-Bus. The SC chip is manufactured on the same 14 nm process as the z14 PU chips, has 17 metal layers, similarly measures 25.3 × 27.5 mm (696 mm2), but consists of 9.7 billion transistors due to amount of L4 memory and runs at half the clock frequency of the PU chip.[3]