TheIBM System/360 architecture is the model independentarchitecture for the entireS/360 line ofmainframe computers, including but not limited to theinstruction set architecture. The elements of the architecture are documented in theIBM System/360 Principles of Operation^[1][2] and theIBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.^[3]

The System/360 architecture provides the following features:

• 1632-bit general-purpose registers
• 4 64-bitfloating-point registers
• 64-bit processor status register (PSW), which includes a 24-bitinstruction address
• 24-bit (16 MB) byte-addressable memory space
• Big-endian byte/word order
• Astandard instruction set, including fixed-point binary arithmetic and logical instructions, present on all System/360 models (except theModel 20, see below).
  • Acommercial instruction set, adding decimal arithmetic instructions, is optional on some models, as is ascientific instruction set, which adds floating-point instructions. Theuniversal instruction set includes all of the above plus the storage protection instructions and is standard for some models.
  • TheModel 44 provides a few unique instructions for data acquisition and real-time processing and is missing the storage-to-storage instructions. However, IBM offered a 'Commercial Instruction Set" feature that ran in bump storage and simulated the missing instructions.
  • TheModel 20 offers a stripped-down version of the standard instruction set, limited to eight general registers with halfword (16-bit) instructions only, plus the commercial instruction set, and unique instructions for input/output.
  • TheModel 67 includes some instructions to handle 32-bit addresses and "dynamic address translation", with additional privileged instructions to provide virtual memory.^[7]

Memory (storage) in System/360 is addressed in terms of8-bit bytes. Various instructions operate on larger units calledhalfword (2 bytes),fullword (4 bytes),doubleword (8 bytes),quad word (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to asbig-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified termword refers to afullword.

The original architecture of System/360 provided for up to 2²⁴ = 16,777,216 bytes of memory. The laterModel 67 extended the architecture to allow up to 2³² = 4,294,967,296^[a] bytes of virtual memory.

System/360 uses truncated addressing similar to that of theUNIVAC III.^[8] That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15^[b] general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic andFloating-point arithmetic features.

• Characters are stored as 8-bit bytes.
• Integers are stored as two's complement binary halfword or fullword values.
• Packed decimal numbers are stored as 1 to 16 8-bit bytes containing an odd number of decimal digits followed by a 4-bit sign. Sign values of hexadecimal A, C, E, and F are positive and sign values of hexadecimal B and D are negative. Digit values of hexadecimal A-F and sign values of 0-9 are invalid, but the PACK and UNPK instructions do not test for validity.
• Zoned decimal numbers are stored as 1 to 16 8-bit bytes, each containing a zone in bits 0-3 and a digit in bits 4-7. The zone of the rightmost byte is interpreted as a sign.
• Floating point numbers are only stored as fullword or doubleword values on older models. On the 360/85^[9] and 360/195^[10] there are also extended precision floating point numbers stored as quadwords. For all three formats, bit 0 is a sign and bits 0-7 are a characteristic (exponent, biased by 64). Bits 8-31 (8-63) are a hexadecimal fraction. For extended precision, the low order doubleword has its own sign and characteristic, which are ignored on input and generated on output.

Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:

• RR (two bytes). Generally byte 1 specifies two 4-bit register numbers, but in some cases, e.g., SVC, byte 1 is a single 8-bit immediate field.
• RS (four bytes). Byte 1 specifies two register numbers; bytes 2-3 specify a base and displacement.
• RX (four bytes). Bits 0-3 of byte 1 specify either a register number or a modifier; bits 4-7 of byte 1 specify the number of the general register to be used as an index; bytes 2-3 specify a base and displacement.
• SI (four bytes). Byte 1 specifies an immediate field; bytes 2-3 specify a base and displacement.
• SS (six bytes). Byte 1 specifies two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length fields is length-1.

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.

TheProgram Status Word (PSW)^{[2]: 71–72} contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks.

Load Program Status Word (LPSW) is a privilegedinstruction that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is most often used to "return" from an interruption by loading the "old" PSW which is associated with the interruption class. Other privileged instructions (e.g., SSM, STNSM, STOSM, SPKA, etcetera) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW; and one non-privileged instruction (SPM) is available for manipulating the program mask.

The architecture^{[2]: 77–83} defines 5 classes ofinterruption. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous^[e] andasynchronous events.

There are two storage fields assigned to each class of interruption on the S/360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW location and then loads the PSW from the new PSW location. This generally replaces the instruction address, thereby effecting a branch, and (optionally) sets and/or resets other fields within the PSW, thereby effecting a mode change.

The S/360 architecture defines a priority to each interruption class, but it is only relevant when two interruptions occur simultaneously; an interruption routine can be interrupted by any other enabled interruption, including another occurrence of the initial interruption. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the "first-level" interruption handlers. "Second-level" interruption handlers are generally designed for stacked interruptions (multiple occurrences of interruptions of the same interruption class).

An I/O interruption^[15] occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also forasynchronous events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into theCSW at location 64 ('40'X).

A Program interruption^{[2]: 16, 79–80.1} occurs when an instruction encounters one^[f] of 15^[g] exceptions; however, if theProgram Mask bit corresponding to an exception is 0 then there is no interruption for that exception. On 360/65,^[21]: 12 360/67^[11]: 46 and 360/85^[9]: 12 the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0.The Interruption code may be any of

• Anoperation exception^[22] is recognized when a program attempts to execute an instruction with an opcode that the computer does not implement. In particular, an operation exception is recognized when a program is written for an optional feature, e.g., floating point, that is not installed.
• Aprivileged operation exception^[22] is recognized when a program attempts to execute a privileged instruction when the problem state bit in the PSW is 1.
• Anexecute exception^[22] is recognized when the operand of anEXECUTE instruction (EX) is another EXECUTE instruction.
• Aprotection exception^[22] is recognized when a program attempts to store into a location whose storage protect key does not match^[j] the PSW key, or to fetch from a fetch protected location whose storage protect key does not match the PSW key.
• Anaddressing exception^[23] is recognized when a program attempts to access a storage location that is not currently available. This normally occurs with an address beyond the capacity of the machine, but it may also occur on machines that allow blocks of storage to be taken offline.
• Aspecification exception^[24] is recognized when an instruction has a length or register field with values not permitted by the operation, or when it has an operand address that does not satisfy the alignment requirements of the opcode, e.g., a LH instruction with an odd operand address on a machine without the byte alignment feature.
• Adata exception^[24] is recognized when a decimal instruction specifies invalid operands, e.g., invalid data, invalid overlap.
• Afixed-point overflow exception^[24] is recognized when significant bits are lost in a fixed point arithmetic or shift instruction, other than divide.
• Afixed-point divide exception^[24] is recognized when significant bits are lost in a fixed point divide or Convert to Binary instruction.
• Adecimal overflow exception^[24] is recognized when significant digits are lost in a decimal arithmetic instruction, other than divide.
• Adecimal divide exception^[24] is recognized when significant bits are lost in a decimal divide instruction. The destination is not altered.
• Anexponent overflow exception^[24] is recognized when the characteristic in a floating-point arithmetic operation exceeds 127 and the fraction is not zero.
• Anexponent underflow exception^[24] is recognized when the characteristic in a floating-point arithmetic operation is negative and the fraction is not zero.
• Asignificance exception^[24] is recognized when the fraction in a floating-point add or subtract operation is zero.
• Afloating-point divide exception^[25] is recognized when the fraction in the divisor of a floating-point divide operation is zero.

A Supervisor Call interruption^[17] occurs as the result of aSupervisor Call instruction; the system stores bits 8-15 of the SVC instruction as the Interruption Code.

An External^[26][k] interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1

A Machine Check interruption^[19] occurs to report unusual conditions associated with the channel or CPU that cannot be reported by another class of interruption. The most important class of conditions causing a Machine Check is a hardware error such as a parity error found in registers or storage, but some models may use it to report less serious conditions. Both the interruption code and the data stored in the scanout area at '80'x (128 decimal) are model dependent.

This article describes I/O from the CPU perspective. It does not discuss the channel cable or connectors, which have aseparate article; there is a summaryelsewhere and details can be found in the IBM literature^[3] and in FIPS PUB 60-2.^[27]

I/O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through360/50) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiplesubchannels, each containing the status of an individual channel program. A subchannel associated with multiple devices that cannot concurrently have channel programs is referred to asshared; a subchannel representing a single device is referred to asunshared.

There are three types of channels on the S/360:

• Abyte multiplexer channel is capable of executing multipleCCWs concurrently; it is normally used to attach slow devices such as card readers and telecommunications lines. A byte multiplexer channel could have a number of selector subchannels, each with only a single subchannel, which behave like low-speed selector channels.
• Aselector channel has only a single subchannel, and hence is only capable of executing one channel command at a time. It is normally used to attach fast devices that are not capable of exploiting a block multiplexer channel to suspend the connection, such as magnetic tape drives.
• Ablock multiplexer channel is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which there is a mechanical delay after completion of data transfer, e.g., for seeks on moving-head DASD. The block multiplexer channel was a late addition to the System/360 architecture; early machines had only byte multiplexer channels and selector channels. The block multiplexer channel is an optional feature only on the models 85 and 195. The block multiplexor channel is also available on the laterSystem/370 computers.

Conceptually peripheral equipment is attached to a S/360 throughcontrol units, which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels thatsteal cycles from the processor.

Peripheral devices are addressed with 16-bit^[l] addresses.,^[2]: 89 referred to ascua orcuu; this article will use the termcuu. The high 8 bits identify a channel, numbered from 0 to 6,^[c] while the low 8 bits identify a device on that channel. A device may have multiplecuu addresses.

Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.

Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.

There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullwordChannel Address Word (CAW). Performing an I/O normally requires the following:

• initializing theCAW with the storage key and the address of the first CCW
• issuing aStart I/O (SIO) instruction that specifies thecuu for the operation
• waiting^[m] for an I/O interruption
• handling any unusual conditions indicated in theChannel Status Word (CSW)

A channel program consists of a sequence ofChannel Control Words (CCWs) chained together (see below.) Normally the channel fetchesCCWs from consecutive doublewords, but a control unit can direct the channel to skip a CCW and aTransfer In Channel (TIC)CCW can direct the channel to start fetchingCCWs from a new location.

There are several defined ways for a channel command to complete. Some of these allow the channel to continue fetching CCWs, while others terminate the channel program. In general, if the CCW does not have the chain-command bit set and is not a TIC, then the channel will terminate the I/O operation and cause an I/O interruption when the command completes. Certain status bits from the control unit suppress chaining.

The most common ways for a command to complete are for the count to be exhausted when chain-data is not set and for the control unit to signal that no more data transfers should be made. If Suppress-Length-Indication (SLI) is not set and one of those occurs without the other, chaining is not allowed. The most common situations that suppress chaining are unit-exception and unit-check. However, the combination of unit-check and status-modifier does not suppress chaining; rather, it causes the channel to do a command retry, reprocessing the same CCW.

In addition to the interruption signal sent to the CPU when an I/O operation is complete, a channel can also send a Program-Controlled interruption (PCI) to the CPU while the channel program is running, without terminating the operation, and a delayed device-end interruption after the I/O completion interruption.

These conditions are detected by the channel and indicated in theCSW.^[28]

• Program-controlled interruption^[29] indicates that the channel has fetched a CCW with the PCI bit set. The channel continues processing; this interruption simply informs the CPU of the channel's progress. An example of the use of Program-controlled interruption is in the "Program Fetch" function of Contents Supervision, whereby the control program is notified that a Control/Relocation Record has been read. To ensure that this record has been completely read into main storage, a "disabled bit spin", one of the few which remains in the control program, is initiated. Satisfaction of the spin indicates that the Control/Relocation Record is completely in main storage and the immediately preceding Text Record may be relocated. After relocation, a NOP CCW is changed to a TIC and the channel program continues. In this way, an entire load module may be read and relocated while utilizing only oneEXCP, and possibly only one revolution of the disk drive. PCI also has applications in teleprocessing access method buffer management.
• Incorrect length^[30] indicates that the data transfer for a command completed before the Count was exhausted. This indication is suppressed if theSuppress-Length-Indication bit in the CCW is set.
• Program check^[30] indicates one of the following errors
  • Nonzero bits where zeros are required
  • An invalid data or CCW address
  • The CAW or a TIC refers to a TIC
• Protection check^[31] indicates that the protection key in the CAW is non-zero and does not match the storage protection key.
• Channel data check^[32] indicates a parity error during a data transfer.
• Channel control check^[32] indicates a channel malfunction other thanChannel data check orInterface control check.
• Interface control check^[32] indicates an invalid signal in the channel to control unit interface.
• Chaining check^[32] indicates lost data during data chaining.

These conditions are presented to the channel by the control unit or device.^[33] In some cases they are handled by the channel and in other cases they are indicated in theCSW. There is no distinction between conditions detected by the control unit and conditions detected by the device.

• Attention^[34] indicates an unusual condition not associated with an ongoing channel program. It often indicates some sort of operator action like requesting input, in which case the CPU would respond by issuing a read-type command, most often a sense command (04h) from which additional information could be deduced. Attention is a special condition, and requires specific operating system support, and for which the operating system has a special attention table^[n] with a necessarily limited number of entries.
• Status modifier^[35] (SM) indicates one of three unusual conditions
  • A Test I/O instruction was issued to a device that does not support it.
  • ABusy status refers to the control unit rather than to the device.
  • A device has detected a condition that requires skipping a CCW. A CCW with a command for which Status Modifier is possible will normally specify command chaining, in which case the SM is processed by the channel and does not cause an interruption.

A typical channel program where SM occurs is

    ...    Search Id Equal    TIC           *-8    Read Data

where the TIC causes the channel to refetch the search until the device indicates a successful search by raising SM.

• Control unit end^[36] indicates that a previous control unit busy status has been cleared.
• Busy^[37] indicates that a device (SM=0) or a control unit (SM=1) is busy.
• Channel end^[38] indicates that the device has completed the data transfer for a channel command. There may also be anIncorrect length indication if the Count field of the CCW is exhausted, depending on the value of theSuppress-Length-Indication bit.
• Device end^[38] indicates that the device has completed an operation and is ready to accept another. DE may be signalled concurrently withCE or may be delayed.
• Unit check^[39] indicates that the device or control unit has detected an unusual condition and that details may be obtained by issuing a Sense command.
• Unit exception^[40] indicates that the device has detected an unusual condition, e.g., end of file.

The fullwordChannel Address Word^[2]: 99 (CAW) contains a 4-bit storage protection key and a 24-bit address of the channel program to be started.

AChannel Command Word is a doubleword containing the following:

• an 8-bit channelCommand Code^[41]
• a 24-bit address^[42]
• a 5-bit flag field^[43]
• an unsigned halfword Count field^[42]

The low order 2 or 4 bits determine the six types of operations that the channel performs;.^{[2]: 100, 105} The encoding is

The meaning of the high order six or four bits, the modifier bits,M in the table above, depends upon the type of I/O device attached, see e.g.,DASDCKD CCWs. All eight bits are sent to and interpreted in the associated control unit (or its functional equivalent).

Control is used to cause a state change in a device or control unit, often associated with mechanical motion, e.g., rewind, seek.

Sense is used to read data describing the status of the device. The most important case is that when a command terminates with unit check, the specific cause can only be determined by doing a Sense and examining the data returned. A Sense command with the modifier bits all zero is always valid.

A noteworthy deviation from the architecture is that DASD use Sense command codes for Reserve and Release, instead of using Control.

The flags in a CCW affect how it executes and terminates.

TheChannel Status Word (CSW)^{[2]: 113–121} provides data associated with an I/O interruption.

• TheProtection Key field contains the protect key from the CAW at the time that the I/O operation was initiated for I/O complete or PCI interruptions.^[53]
• TheCommand Address field contains the address+8 of the last CCW fetched for an I/O complete or PCI interruption. However, there are 9 exceptions^[53]
• TheStatus field contains one byte ofChannel status bits, indicating conditions detected by the channel^[28] and one byte ofUnit status bits, indicating conditions detected by the I/O unit^[33] There is no distinction between conditions detected by the control unit and conditions detected by the device.
• TheResidual Count is a half word that gives the number of bytes in the area described by the CCW that have not been transferred to or from the channel^[55] The difference between the count in the CCW and the residual count gives the number of bytes transferred.

The S/360 has four^[56] I/O instructions: Start I/O (SIO), Test I/O (TIO), Halt I/O (HIO) and Test Channel (TCH). All four are privileged and thus will cause a privileged operation program interruption if used in problem state. The B₁ (base) and D₁ (displacement) fields are used to calculate the cuu (channel and device number); bits 8-15 of the instructions are unused and should be zero for compatibility with the S/370.

SIO^[57] attempts to start the channel program pointed to by theCAW, using the storage protection key in the CAW.

TIO^[58] tests the status of a channel and device. It may also store aCSW, in which case it completes with condition code 1.

HIO^[59] attempt to terminate an active channel program. It may also store aCSW, in which case it completes with condition code 1.

TCH^[60] tests the status of a channel. It does not affect the status of an active channel program and does not store aCSW,

The architecture of System/360 specified the existence of several common functions, but did not specify their means of implementation. This allowed IBM to use different physical means, e.g., dial, keyboard, pushbutton, roller, image or text on a CRT, for selecting the functions and values on different processors. Any reference tokey orswitch should be read as applying to, e.g., a light-pen selection, an equivalent keyboard sequence.

• System Reset sends a reset signal on every I/O channel and clears the processor state; all pending interruptions are cancelled. System Reset is not guaranteed to correct parity errors in general registers, floating point registers or storage. System Reset does not reset the state of shared I/O devices.
• Initial Program Load (IPL)^[61] is a process for loading a program when there isn't a loader available in storage, usually because the machine was just powered on or to load an alternative operating system.^[2]: 123 This process is sometimes known asBooting.

As part of the IPL facility the operator has a means of specifying a 12-bit^[c] device address, typically with three dials as shown in the operator controls drawing. When the operator^[p] selects theLoad function, the system performs aSystem Reset, sends a Read IPL^[q] channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetchingCCWs at location 8; the effect is as if the channel had fetched a CCW from location 0 with a length of 24, an address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at location 2 and loads the PSW from location 0.

Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.

• Emergency pull switch^[62] (Emergency power off, EPO) sends an EPO signal to every I/O channel, then turns off power to the processor complex. Because EPO bypasses the normal sequencing of power down, damage can result, and the EPO control has a mechanical latch to ensure that a customer engineer inspects the equipment before attempting to power it back on.
• Power on^[62] powers up all components of the processor complex and performs a system reset.
• Power off^[62] initiates an orderly power-off sequence. Although the contents of storage are preserved, the associated storage keys may be lost.
• TheInterrupt key^[62] causes anexternal interruption with bit 25 set in the External Old PSW.
• TheWait light^[62] indicates that thePSW has bit 14 (wait) set; the processor is temporarily halted but resumes operation when an interruption condition occurs.
• TheManual light^[62] indicates that the CPU is in a stopped state.
• TheSystem light^[62] indicates that a meter is running, either due to CPU activity or due to I/O channel activity.
• TheTest light^[62] indicates that certain operator controls are active, when certain facilities, e.g., INSTRUCTION STEP, have been used by a Diagnose instruction or when abnormal thermal conditions exist. The details are model dependent.
• TheLoad light^[62] is turned on by IPL and external start. It is turned off by loading the PSW from location 0 at the completion of the load process.
• TheLoad unit^[63] controls provide the rightmost 11^[r] bits of the device from which to perform an IPL.
• TheLoad Key^[64] starts theIPL sequence.
• ThePrefix Select Key Switch^[64] selects whetherIPL will use the primary prefix or the alternative prefix.
• TheSystem-Reset Key^[64] initiates aSystem Reset.
• TheStop Key^[64] puts the CPU in a stopped state; channel programs continue running and interruption conditions remain pending.
• TheRate Switch^[64] determines the mode in which the processor fetches instructions. Two modes are defined by the architecture:
  • PROCESS
  • INSTRUCTION STEP
• TheStart Key^[64] initiates instruction fetching in accordance with the setting of theRate Switch.
• TheStorage-Select Switch^[65] determines the type of resource accessed by theStore Key andDisplay Key. Three selections are defined by the architecture:
  • Main storage
  • General registers
  • Floating-point registers
• TheAddress Switches^[65] specify the address or register number for theStore Key,Display Key and, on some models, theSet IC Key..
• TheData Switches^[65] specify the data for theStore Key and, on some models, theSet IC Key.
• TheStore Key^[65] stores the value in theData Switches as specified by theStorage-Select Switch and theAddress Switches.
• TheDisplay Key^[65] displays the value specified by theStorage-Select Switch and theAddress Switches.
• TheSet IC=^[65] sets the instruction address portion of the PSW from theData Switches or theAddress Switches, depending on the model.
• TheAddress-Compare Switches^[65] select the mode of comparison and what is compared. Stop on instruction address compare is present on all models, but stop on data address compare is only present on some models.
• TheAlternate-Prefix Light^[65] is on when the prefix trigger is in the alternate state.

On some models, e.g., theS/360-85,^[9] the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs depending on receiving a program check type 6 (alignment) on those instructions must be modified.

The decimal arithmetic feature provides instructions that operate on packed decimal data. A packed decimal number has 1-31 decimal digits followed by a 4-bit sign. All of the decimal arithmetic instructions except PACK and UNPACK generate a Data exception if a digit is not in the range 0-9 or a sign is not in the range A-F.

TheDirect Control^[66] feature provides six external signal lines and an 8-bit data path to/from storage.^[67]

The floating-point arithmetic feature provides 4 64-bit floating point registers and instructions to operate on 32 and 64 bit hexadecimal floating point numbers. The 360/85 and 360/195 also support 128 bit extended precision floating point numbers.

If the interval timer feature^[2]: 17.1 is installed, the processor decrements the word at location 80 ('50'X) at regular intervals; the architecture does not specify the interval but does require that value subtracted make it appear as though 1 were subtracted from bit 23 300 times per second. The smaller models decremented at the same frequency (50 Hz or 60 Hz) as the AC power supply, but larger models had a high resolution timer feature. The processor causes an External interruption when the timer goes to zero.

Multi-system operation^[68] is a set of features to support multi-processor systems, e.g.,Direct Control, direct address relocation (prefixing).

If the storage protection feature^{[2]: 17-17.1} is installed, then there is a 4-bit storage key associated with every 2,048-byte block of storage and that key is checked when storing into any address in that block by either a CPU or an I/O channel. A CPU or channel key of 0 disables the check; a nonzero CPU or channel key allows data to be stored only in a block with the matching key.

Storage Protection was used to prevent a defective application from writing over storage belonging to the operating system or another application. This permitted testing to be performed along with production. Because the key was only four bits in length, the maximum number of different applications that could be run simultaneously was 15.

An additional option available on some models was fetch protection. It allowed the operating system to specify that blocks were protected from fetching as well as from storing.

TheSystem/360 Model 20 is radically different and should not be considered to be a S/360.

TheSystem/360 Model 44 is missing certain instructions, but a feature allowed the missing instructions to be simulated in hidden memory thus allowing the use of standard S/360 operating systems and applications.

Some models have features that extended the architecture, e.g., emulation instructions, paging, and some models make minor deviations from the architecture. Examples include:

• The multisystem feature on the S/360-65 which modifies the behavior of the direct control feature and of the Set System Mask (SSM) instruction.^[21]
• TheSystem/360 Model 67-2 had similar, but incompatible, changes.^[11]

Some deviations served as prototypes for features of theS/370 architecture.

• Memory protection key

S360

IBM System/360 Principles of Operation. Systems Reference Library (Eighth ed.). IBM. September 1968. A22-6821-7.

• Prasad, N.S. (1989).IBM Mainframes. McGraw-Hill.ISBN 0070506868. — Chapter 3 (pp. 41–110) describes the System/360 architecture.
• Greiner, Dan (August 10, 2011)."IBM z/Architecture CPU Features - A Historical Perspective"(PDF).Evolution of The IBM Mainframe Architecture.SHARE 117 in Orlando.SHARE. Session 9220. RetrievedFebruary 7, 2023.

• Introduction to IBM System/360 Architecture (Student Text)

• Computing platforms
• IBM System/360 mainframe line
• Computer architecture
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