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 System/360 Model 44 front panel | |
| Manufacturer | International Business Machines Corporation (IBM) |
|---|---|
| Product family | System/360 |
| Released | August 16, 1965 (1965-08-16) |
| Discontinued | September 23, 1973 (1973-09-23) |
| Memory | 32–256 KB Core |
TheIBM System/360 Model 44 is a specialized member of theIBM System/360 family, with a variant of the System/360computer architecture, designed for scientific computing,real-time computing,process control andnumerical control (NC).[note 1]
The Model 44 was announced August 16, 1965 and withdrawn September 24, 1973.[1]
The base Model 44 lacks the storage-to-storage character and decimal instruction sets of a standard System/360,[2] however an "extended instruction set" feature was available to provide the missing instructions.[1] The machine features four unique instructions:Change Priority Mask (CHPM),Load PSW Special (LPSX),Read Direct Word (RDDW), andWrite Direct Word (WRDW).[2]: p.73
The system comes with four memory sizes: E (32 KiB), F (64 KiB), G (128 KiB), and H (256 KiB), with an access time of 1 μs, which puts it closer to theModel 65 (.75 μs) than theModel 50 (2.0 μs).[3]: pp.6-11, 6–12 [1]Storage protection is an optional feature.[4]: p.9
General purpose registers are normally located in a non-addressable portion of 1 μs core storage termed "bump storage". For added speed, the general purpose registers can be implemented inSolid Logic Technology (SLT) circuitry with an access time of .25 μs.[4]: p.8
A unique feature of the Model 44 is "variable-length precision floating point arithmetic".It has the same short floating-point instructions and long floating-point instructions as the other models in the System/360 line, but it also has a rotary switch on the front panel which can be used to set the precision of long floating-point numbers. The mantissa portion of long floating-point numbers can be chosen as 32, 40, 48, or 56 bits, with 56 bits being the standard value. Whatever the setting, long floating-point numbers still occupy 64 bits in memory (the first eight bits are the sign and the exponent); the setting only leads, when it was less than 56 bits, to long floating-point operations ignoring some of the least significant bits of these numbers. This provides an improvement in speed when greater precision is not needed.[4]: p.13
An optional feature providessix external interrupt lines.[4]: p.9
Thedirect word feature allows the transfer of a full 32-bit word of information between an external device and main storage. This differs from the standard System/360direct control feature which transfers a single byte. TheWrite Direct Word instruction places the contents of a word in memory as static signals on the 32 direct-out lines and uses the I2 field of the instruction as up to eight timing pulses. TheRead Direct Word reads the 32 direct-in lines into memory and sends the I2 field as timing pulses.[5]: p.5
Write Direct Word ('B4'x): WRDW D1(B1),I2
Read Direct Word ('B5'x): RDDW D1(B1),I2
Thedirect data channel feature provides a fast, simple data transfer capability. Controlled by standard System/360 I/O instructions and commands, it allows the connection of external devices that perform word-by-word data transfers with the Model 44 CPU at transfer rates up to 4 MiB/s.[5]: pp.12–16
Thepriority interrupt feature adds thirty-two interrupt levels to the standard five. This uses locations '800'x to '9FF'x for the old and new program status word locations. An eight bit interrupt description from the interrupting device is stored in bit positions 24 to 31 of the correspondingold PSW. Bits 16-23 of thenew PSW are used as a mask which is XORed with the interrupt description to modify the address from thenew PSW, effectively allowing indexing into a jump table for the interrupt according to data sent by the device. The interrupts are numbered from 0 (highest priority) to 31 (lowest); a higher priority interrupt can interrupt processing of a lower priority. A 32 bitPriority Mask Register, set by theChange Priority Mask instruction, can be used to selectively mask interrupts to keep them in pending status until the mask is reset. The instruction can enable levels tagged by 1 bits, disable levels tagged by 0 bits cancel levels tagged by 1 bits, or cancel and enable levels tagged by 1 bits depending on the value of the I2 field. TheLoad PSW Special instruction is used to exit an interrupt routine resume the next highest priority routine or non-interrupt code.[5]: pp.17–21
Load PSW Special ('B2'x): LPSX D1(B1),I2
I2 is reserved and should be zero.
Change Priority Mask ('B3'x): CHPM D1(B1),I2
The high order two bits of the I2 field are called themask bitand thecancel bit.
The remainder of the I2 field is reserved and should be zero.
(mask bit) (cancel bit) Function 1 0 Enable levels tagged by 1 bits 0 0 Disable levels tagged by 0 bits 0 1 Cancel levels tagged by 1 bits 1 1 Cancel and enable levels tagged by 1 bits
The Model 44 can support up to one standard and two high-speed System/360multiplexer channels in addition to integrated adapters for thesingle disk storage and the console1052 printer/keyboard.[1]
A unique feature of the Model 44 is its integrated single disk storage drive which uses theIBM 2315 cartridge and provides 1,171,200 bytes[4]: pp.5, 11 of removable disk storage built right into the CPU. A second integrated drive is available as an option.[4]: p.12 TheModel 44 Programming System (M44PS) uses this drive as a systems residence device.[6]: p.7
TheModel 44 Programming System software includes a supervisor,utility programs,assembler,FORTRAN IV compiler, and a library of scientific subroutines.[1]
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