Afield-programmable gate array (FPGA) is a type of configurableintegrated circuit that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to asprogrammable logic devices (PLDs). They consist of a grid-connected array ofprogrammablelogic blocks that can be configured "in the field" to interconnect with other logic blocks to perform various digital functions. FPGAs are often used in limited (low) quantity production of custom-made products, and in research and development, where the higher cost of individual FPGAs is not as important and where creating and manufacturing a custom circuit would not be feasible. Other applications for FPGAs include the telecommunications, automotive, aerospace, and industrial sectors, which benefit from their flexibility, high signal processing speed, and parallel processing abilities.
A FPGA configuration is generally written using ahardware description language (HDL) e.g.VHDL, similar to the ones used forapplication-specific integrated circuits (ASICs).Circuit diagrams were formerly used to write the configuration.
The logic blocks of an FPGA can be configured to perform complexcombinational functions, or act as simplelogic gates likeAND andXOR. In most FPGAs, logic blocks also includememory elements, which may be simpleflip-flops or more sophisticated blocks of memory.[1] Many FPGAs can be reprogrammed to implement differentlogic functions, allowing flexiblereconfigurable computing as performed incomputer software.
FPGAs also have a role inembedded system development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.[2]
FPGAs are also commonly used during the development of ASICs to speed up the simulation process.
The FPGA industry sprouted fromprogrammable read-only memory (PROM) andprogrammable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable).[3]
Altera was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on thedie to erase theEPROM cells that held the device configuration.[4]
Xilinx produced the first commercially viable field-programmablegate array in 1985[3] – the XC2064.[5] The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.[6] The XC2064 had 64 configurable logic blocks (CLBs), with two three-inputlookup tables (LUTs).[7]
In 1987, theNaval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[3]
Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s when competitors sprouted up, eroding a significant portion of their market share. By 1993, Actel (laterMicrosemi, nowMicrochip) was serving about 18 percent of the market.[6]
The 1990s were a period of rapid growth for FPGAs, both in circuit sophistication and the volume of production. In the early 1990s, FPGAs were primarily used intelecommunications andnetworking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.[8]
By 2013, Altera (31 percent), Xilinx (36 percent) and Actel (10 percent) together represented approximately 77 percent of the FPGA market.[9]
Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like thedata centers that operate theirBing search engine), due to theperformance per watt advantage FPGAs deliver.[10] Microsoft began using FPGAs toaccelerate Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for theirAzurecloud computing platform.[11]
Since 2019, modern generation of FPGAs have been integrated with other architectures likeAI engines to target workloads in artificial intelligence domain.[12]
The following timelines indicate progress in different aspects of FPGA design.
Adesign start is a new custom design for implementation on an FPGA.
Contemporary FPGAs have amplelogic gates and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that anASIC can perform. The ability to update the functionality after shipping,partial re-configuration of a portion of the design[19] and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.[1]
As FPGA designs employ very fast I/O rates and bidirectional databuses, it becomes a challenge to verify correct timing of valid data within setup time and hold time.[20]Floor planning helps resource allocation within FPGAs to meet these timing constraints.
Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmableslew rate on each output pin. This allows the user to set low rates on lightly loaded pins that would otherwisering orcouple unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.[21][22] Also common are quartz-crystal oscillator driver circuitry, on-chipRC oscillators, andphase-locked loops with embeddedvoltage-controlled oscillators used for clock generation and management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differentialcomparators on input pins designed to be connected todifferential signaling channels. A fewmixed signal FPGAs have integrated peripheralanalog-to-digital converters (ADCs) anddigital-to-analog converters (DACs) with analog signal conditioning blocks, allowing them to operate as asystem on a chip (SoC).[23] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, andfield-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.
The most common FPGA architecture consists of an array oflogic blocks called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor),I/O pads, and routing channels.[1] Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.
"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, acrossbar switch requires much more routing than asystolic array with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms oflookup tables (LUTs) and I/Os can berouted. This is determined by estimates such as those derived fromRent's rule or by experiments with existing designs."[24]
In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, afull adder (FA) and aD-type flip-flop. The LUT might be split into two 3-input LUTs. Innormal mode those are combined into a 4-input LUT through the firstmultiplexer (mux). Inarithmetic mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be eithersynchronous orasynchronous, depending on the programming of the third mux. In practice, the entire adder or parts of it arestored as functions into the LUTs in order to savespace.[25][26][27]
Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these includemultipliers, genericDSP blocks,embedded processors, high-speed I/O logic and embeddedmemories.
Higher-end FPGAs can contain high-speedmulti-gigabit transceivers andhard IP cores such asprocessor cores,Ethernetmedium access control units,PCI orPCI Express controllers, and externalmemory controllers. These cores exist alongside the programmable fabric, but they are built out oftransistors instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performancesignal conditioning circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such asline coding may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
An alternate approach to using hard macro processors is to make use ofsoft processorIP cores that are implemented within the FPGA logic.Nios II,MicroBlaze andMico32 are examples of popular softcore processors. Many modern FPGAs are programmed atrun time, which has led to the idea ofreconfigurable computing or reconfigurable systems –CPUs that reconfigure themselves to suit the task at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
In 2012 the coarse-grained architectural approach was taken a step further by combining thelogic blocks and interconnects of traditional FPGAs with embeddedmicroprocessors and related peripherals to form a completesystem on a programmable chip. Examples of such hybrid technologies can be found in theXilinx Zynq-7000 allprogrammable SoC,[28] which includes a 1.0 GHz dual-coreARM Cortex-A9 MPCore processorembedded within the FPGA's logic fabric,[29] or in theAltera Arria V FPGA, which includes an 800 MHzdual-coreARM Cortex-A9 MPCore. TheAtmel FPSLIC is another such device, which uses anAVR processor in combination with Atmel's programmable logic architecture. TheMicrosemiSmartFusion devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB offlash and 64 kB of RAM) and analogperipherals such as a multi-channelanalog-to-digital converters anddigital-to-analog converters in theirflash memory-based FPGA fabric.[citation needed]
Most of the logic inside of an FPGA issynchronous circuitry that requires aclock signal. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as anH tree, so they can be delivered with minimalskew. FPGAs may contain analogphase-locked loop ordelay-locked loop components to synthesize newclock frequencies and managejitter. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separateclock domains. These clock signals can be generated locally by an oscillator or they can be recovered from adata stream. Care must be taken when buildingclock domain crossing circuitry to avoidmetastability. Some FPGAs containdual port RAM blocks that are capable of working with different clocks, aiding in the construction of buildingFIFOs and dual port buffers that bridge clock domains.
To shrink the size and power consumption of FPGAs, vendors such asTabula andXilinx have introduced3D or stacked architectures.[30][31] Following the introduction of its28 nm 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.
Xilinx's approach stacks several (three or four) active FPGA dies side by side on a siliconinterposer – a single piece of silicon that carries passive interconnect.[31][32] The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called aheterogeneous FPGA.[33]
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.[34]
To define the behavior of the FPGA, the user provides a design in ahardware description language (HDL) or as aschematic design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and itscomponent modules.
Using anelectronic design automation tool, a technology-mappednetlist is generated. The netlist can then be fit to the actual FPGA architecture using a process calledplace and route, usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results usingtiming analysis,simulation, and otherverification and validation techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via aserial interface (JTAG) or to an external memory device such as anEEPROM.
The most common HDLs areVHDL andVerilog.National Instruments'LabVIEW graphical programming language (sometimes referred to asG) has an FPGA add-in module available to target and program FPGA hardware. Verilog was created to simplify the process making HDL more robust and flexible. Verilog has a C-like syntax, unlike VHDL.[35][self-published source?]
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly calledintellectual property (IP) cores, and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such asOpenCores (typically released underfree and open source licenses such as theGPL,BSD or similar license). Such designs are known asopen-source hardware.
In a typicaldesign flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially theRTL description inVHDL orVerilog is simulated by creatingtest benches to simulate the system and observe results. Then, after thesynthesis engine has mapped the design to a netlist, the netlist is translated to agate-level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally, the design is laid out in the FPGA at which pointpropagation delay values can beback-annotated onto the netlist, and the simulation can be run again with these values.
More recently,OpenCL (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in theC programming language.[36] For further information, seehigh-level synthesis andC to HDL.
Most FPGAs rely on anSRAM-based approach to be programmed. These FPGAs are in-system programmable and re-programmable, but require external boot devices. For example,flash memory orEEPROM devices may load contents into internal SRAM that controls routing and logic. The SRAM approach is based onCMOS.
Rarer alternatives to the SRAM approach include:
In 2016, long-time industry rivalsXilinx (now part ofAMD) andAltera (now part ofIntel) were the FPGA market leaders.[38] At that time, they controlled nearly 90 percent of the market.
Both Xilinx and Altera provideproprietaryelectronic design automation software forWindows andLinux (ISE/Vivado andQuartus) which enables engineers todesign, analyze,simulate, andsynthesize (compile) their designs.[39][40]
In March 2010,Tabula announced their FPGA technology that usestime-multiplexed logic and interconnect that claims potential cost savings for high-density applications.[41] On March 24, 2015, Tabula officially shut down.[42]
On June 1, 2015, Intel announced it would acquire Altera for approximatelyUS$16.7 billion and completed the acquisition on December 30, 2015.[43]
On October 27, 2020, AMD announced it would acquire Xilinx[44] and completed the acquisition valued at about US$50 billion in February 2022.[45]
In February 2024 Altera became independent of Intel again.[46]
Other manufacturers include:
An FPGA can be used to solve any problem which iscomputable. FPGAs can be used to implement asoft microprocessor, such as the XilinxMicroBlaze or AlteraNios II. But their advantage lies in that they are significantly faster for some applications because of theirparallel nature andoptimality in terms of the number of gates used for certain processes.[52]
FPGAs were originally introduced as competitors tocomplex programmable logic devices (CPLDs) to implementglue logic forprinted circuit boards. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as fullsystems on chips (SoCs). Particularly with the introduction of dedicatedmultipliers into FPGA architectures in the late 1990s, applications that had traditionally been the sole reserve ofdigital signal processors (DSPs) began to use FPGAs instead.[53][54]
The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.[55][56] The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.
Another trend in the use of FPGAs ishardware acceleration, where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engineBing is noted for adopting FPGA acceleration for its search algorithm in 2014.[57] As of 2018[update], FPGAs are seeing increased use asAI accelerators including Microsoft's Project Catapult[11] and for acceleratingartificial neural networks formachine learning applications.
Originally,[when?] FPGAs were reserved for specificvertical applications where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.[citation needed]
Other uses for FPGAs include:
FPGAs play a crucial role in modern military communications, especially in systems like theJoint Tactical Radio System (JTRS) and in devices from companies such asThales andHarris Corporation. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.[64]
Concerninghardware security, FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors. FPGAs' flexibility makes malicious modifications duringfabrication a lower risk.[65] Previously, for many FPGAs, the designbitstream was exposed while the FPGA loads it from external memory, typically during powerup. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstreamencryption andauthentication. For example,Altera andXilinx offerAES encryption (up to 256-bit) for bitstreams stored in an external flash memory.Physical unclonable functions (PUFs) are integrated circuits that have their own unique signatures and can be used to secure FPGAs while taking up very little hardware space.[66]
FPGAs that store their configuration internally in nonvolatile flash memory, such asMicrosemi's ProAsic 3 orLattice's XP2 programmable devices, do not expose the bitstream and do not needencryption. Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such asMicrosemi.
With its Stratix 10 FPGAs and SoCs,Altera introduced a Secure Device Manager andphysical unclonable functions to provide high levels of protection against physical attacks.[67]
In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a criticalbackdoor vulnerability had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto andaccess keys, accessing unencrypted bitstream, modifyinglow-level silicon features, and extractingconfiguration data.[68]
In 2020 a critical vulnerability (named Starbleed) was discovered in all Xilinx 7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.[citation needed]
Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.[69]
Advantages of FPGAs include the ability to reprogram equipment in the field to fixbugs or make other improvements. Some FPGAs have the capability ofpartial re-configuration that lets one portion of the device be re-programmed while other portions continue running.[70][71] Other advantages may include shortertime to market and lowernon-recurring engineering costs. Vendors can also take a middle road viaFPGA prototyping: developing their prototype hardware on FPGAs, but manufacturing their final version as an ASIC after the design has been committed. This is often also the case with new processor designs.[72]
The primary differences between CPLDs and FPGAs arearchitectural. A CPLD has a comparatively restrictive structure consisting of one or more programmablesum-of-products logic arrays feeding a relatively small number of clockedregisters. As a result, CPLDs are less flexible but have the advantage of more predictablepropagation delay. FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible but also far more complex to design for, or at least requiring more complexelectronic design automation (EDA) software. Another distinction between FPGAs and CPLDs is one of size, as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complexembedded functions such asadders,multipliers,memory, andserializer/deserializers. Another common distinction is that CPLDs contain embeddedflash memory to store their configuration, while FPGAs typically store their configuration in SRAM and require externalnon-volatile memory to initialize it on powerup. When a design requires simple instant-on, CPLDs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions.[73]
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