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Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by theHP–Intel alliance^[1] to describe acomputing paradigm that researchers had been investigating since the early 1980s.^[2] This paradigm is also calledIndependence architectures. It was the basis forIntel andHP development of the IntelItanium architecture,^[3] andHP later asserted that "EPIC" was merely an old term for the Itanium architecture.^[4] EPIC permits microprocessors to execute software instructions in parallel by using thecompiler, rather than complex on-die circuitry, to control parallel instruction execution. This was intended to allow simple performance scaling without resorting to higherclock frequencies.

By 1989, researchers at HP recognized thatreduced instruction set computer (RISC) architectures were reaching a limit at oneinstruction per cycle.^{[clarification needed]} They began an investigation into a new architecture, later namedEPIC.^[3] The basis for the research wasVLIW, in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the softwarecompiler, which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploitinstruction-level parallelism (ILP) by using the compiler to find and exploit additional opportunities forparallel execution.

VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:

• VLIWinstruction sets are notbackward compatible between implementations. Whenwider implementations (moreexecution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
• Load responses from amemory hierarchy which includesCPU caches andDRAM do not have a deterministic delay.^[why?] This makes static scheduling of load instructions by the compiler very difficult.

EPIC architecture evolved from VLIW architecture, but retained many concepts of thesuperscalar architecture.

EPIC architectures add several features to get around the deficiencies ofVLIW:

• Each group of multiple software instructions is called abundle. Each of the bundles has astop bit indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.
• A software prefetch instruction is used as a type of data prefetch. This prefetch increases the chances for a cache hit for loads, and can indicate the degree of temporal locality needed in various levels of the cache.
• A speculative load instruction is used to speculatively load data before it is known whether it will be used (bypassing control dependencies), or whether it will be modified before it is used (bypassing data dependencies).
• A check load instruction aids speculative loads by checking whether a speculative load was dependent on a later store, and thus must be reloaded.

TheEPIC architecture also includes agrab-bag of architectural concepts to increaseILP:

• Predicated execution is used to decrease the occurrence of branches and to increase thespeculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
• Delayed exceptions, using anot a thing bit within the general purpose registers, allow speculative execution past possible exceptions.
• Very large architecturalregister files avoid the need forregister renaming.
• Multi-way branch instructions improve branch prediction by combining many alternative branches into one bundle.

TheItanium architecture also addedrotating register files, a tool useful forsoftware pipelining since it avoids having to manuallyunroll and rename registers.

There have been other investigations into EPIC architectures that are not directly tied to the development of the Itanium architecture:

• TheIMPACT project atUniversity of Illinois at Urbana–Champaign, led byWen-mei Hwu, was the source of much influential research on this topic.
• ThePlayDoh architecture from HP-labs was another major research project.
• Gelato was an open source development community in which academic and commercial researchers worked to develop more effective compilers for Linux applications running on Itanium servers.

• Complex instruction set computer (CISC)
• Reduced instruction set computer (RISC)
• Minimal instruction set computer (MISC)
• Very long instruction word (VLIW)
• No instruction set computing
• One-instruction set computer
• Computer architecture
• Superscalar
• Wide-issue

• Historical background for EPIC
• Mark Smotherman (2002) "Understanding EPIC Architectures and Implementations"

• Instruction processing
• Very long instruction word computing

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