Adigital signal processor (DSP) is a specializedmicroprocessor chip, with its architecture optimized for the operational needs ofdigital signal processing.[1]: 104–107 [2] DSPs arefabricated onmetal–oxide–semiconductor (MOS)integrated circuit chips.[3][4] They are widely used inaudio signal processing,telecommunications,digital image processing,radar,sonar andspeech recognition systems, and in commonconsumer electronic devices such asmobile phones,disk drives andhigh-definition television (HDTV) products.[3]
The goal of a DSP is usually to measure, filter or compress continuous real-worldanalog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such asmobile phones because of power consumption constraints.[5] DSPs often use specialmemory architectures that are able to fetch multiple data or instructions at the same time.
Digital signal processing (DSP)algorithms typically require a large number of mathematical operations to be performed quickly and repeatedly on a series of data samples. Signals (perhaps from audio or video sensors) are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints onlatency; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.
Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power efficiency constraints.[5] A specialized DSP, however, will tend to provide a lower-cost solution, with better performance, lower latency, and no requirements for specialised cooling or large batteries.[citation needed]
Such performance improvements have led to the introduction of digital signal processing in commercialcommunications satellites where hundreds or even thousands of analog filters, switches, frequency converters and so on are required to receive and process theuplinked signals and ready them fordownlinking, and can be replaced with specialised DSPs with significant benefits to the satellites' weight, power consumption, complexity/cost of construction, reliability and flexibility of operation. For example, the SES-12 and SES-14 satellites from operatorSES launched in 2018, were both built byAirbus Defence and Space with 25% of capacity using DSP.[6]
The architecture of a DSP is optimized specifically for digital signal processing. Most also support some of the features of an applications processor or microcontroller, since signal processing is rarely the only task of a system. Some useful features for optimizing DSP algorithms are outlined below.
By the standards of general-purpose processors, DSP instruction sets are often highly irregular; while traditional instruction sets are made up of more general instructions that allow them to perform a wider variety of operations, instruction sets optimized for digital signal processing contain instructions for common mathematical operations that occur frequently in DSP calculations. Both traditional and DSP-optimized instruction sets are able to compute any arbitrary operation but an operation that might require multipleARM orx86 instructions to compute might require only one instruction in a DSP optimized instruction set.
One implication for software architecture is that hand-optimizedassembly-coderoutines (assembly programs) are commonly packaged into libraries for re-use, instead of relying on advanced compiler technologies to handle essential algorithms. Even with modern compiler optimizations hand-optimized assembly code is more efficient and many common algorithms involved in DSP calculations are hand-written in order to take full advantage of the architectural optimizations.
DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as theHarvard architecture or Modifiedvon Neumann architecture, which use separate program and data memories (sometimes even concurrent access on multiple data buses).
DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance[clarification needed]. In addition, extensive use ofDMA is employed.
DSPs frequently use multi-tasking operating systems, but have no support forvirtual memory or memory protection. Operating systems that use virtual memory require more time forcontext switching amongprocesses, which increases latency.
In 1976, Richard Wiggins proposed theSpeak & Spell concept to Paul Breedlove, Larry Brantingham, and Gene Frantz atTexas Instruments' Dallas research facility. Two years later in 1978, they produced the first Speak & Spell, with the technological centerpiece being theTMS5100,[15] the industry's first digital signal processor. It also set other milestones, being the first chip to use linear predictive coding to performspeech synthesis.[16] The chip was made possible with a7 μmPMOSfabrication process.[17]
In 1978,American Microsystems (AMI) released the S2811.[3][4] The AMI S2811 "signal processing peripheral", like many later DSPs, has a hardware multiplier that enables it to domultiply–accumulate operation in a single instruction.[18] The S2281 was the firstintegrated circuit chip specifically designed as a DSP, and fabricated using vertical metal oxide semiconductor (VMOS, V-groove MOS), a technology that had previously not been mass-produced.[4] It was designed as a microprocessor peripheral, for theMotorola 6800,[3] and it had to be initialized by the host. The S2811 was not successful in the market.
In 1979,Intel released the2920 as an "analog signal processor".[19] It had an on-chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market.
In 1980, the first stand-alone, complete DSPs –Nippon Electric Corporation'sNEC μPD7720 based on the modified Harvard architecture[20] andAT&T'sDSP1 – were presented at theInternational Solid-State Circuits Conference '80. Both processors were inspired by the research inpublic switched telephone network (PSTN)telecommunications. The μPD7720, introduced forvoiceband applications, was one of the most commercially successful early DSPs.[3]
The Altamira DX-1 was another early DSP, utilizing quad integer pipelines with delayed branches and branch prediction.[citation needed]
Another DSP produced by Texas Instruments (TI), theTMS32010 presented in 1983, proved to be an even bigger success. It was based on the Harvard architecture, and so had separate instruction and data memory. It already had a special instruction set, with instructions like load-and-accumulate or multiply-and-accumulate. It could work on 16-bit numbers and needed 390 ns for a multiply–add operation. TI is now the market leader in general-purpose DSPs.
About five years later, the second generation of DSPs began to spread. They had 3 memories for storing two operands simultaneously and included hardware to acceleratetight loops; they also had an addressing unit capable of loop-addressing. Some of them operated on 24-bit variables and a typical model only required about 21 ns for a MAC. Members of this generation were for example the AT&T DSP16A or theMotorola 56000.
The main improvement in the third generation was the appearance of application-specific units and instructions in the data path, or sometimes as coprocessors. These units allowed direct hardware acceleration of very specific but complex mathematical problems, like the Fourier-transform or matrix operations. Some chips, like the Motorola MC68356, even included more than one processor core to work in parallel. Other DSPs from 1995 are the TI TMS320C541 or the TMS 320C80.
The fourth generation is best characterized by the changes in the instruction set and the instruction encoding/decoding. SIMD extensions were added, and VLIW and the superscalar architecture appeared. As always, the clock-speeds have increased; a 3 ns MAC now became possible.
Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, (E)DMA circuitry, and a wider bus system. Not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300.
Texas Instruments produces theC6000 series DSPs, which have clock speeds of 1.2 GHz and implement separate instruction and data caches. They also have an 8 MiB 2nd level cache and 64 EDMA channels. The top models are capable of as many as 8000 MIPS (millions of instructions per second), use VLIW (very long instruction word), perform eight operations per clock-cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc). TMS320C6474 chips each have three such DSPs, and the newest generation C6000 chips support floating point as well as fixed point processing.
Freescale produces a multi-core DSP family, the MSC81xx. The MSC81xx is based on StarCore Architecture processors and the latest MSC8144 DSP combines four programmable SC3400 StarCore DSP cores. Each SC3400 StarCore DSP core has a clock speed of 1 GHz.
XMOS produces a multi-core multi-threaded line of processor well suited to DSP operations, They come in various speeds ranging from 400 to 1600 MIPS. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. Threads communicate between each other with buffered channels that are capable of up to 80 Mbit/s. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs
CEVA, Inc. produces and licenses three distinct families of DSPs. Perhaps the best known and most widely deployed is the CEVA-TeakLite DSP family, a classic memory-based architecture, with 16-bit or 32-bit word-widths and single or dualMACs. The CEVA-X DSP family offers a combination of VLIW and SIMD architectures, with different members of the family offering dual or quad 16-bit MACs. The CEVA-XC DSP family targetsSoftware-defined Radio (SDR) modem designs and leverages a unique combination of VLIW and Vector architectures with 32 16-bit MACs.
Analog Devices produce theSHARC-based DSP and range in performance from 66 MHz/198MFLOPS (million floating-point operations per second) to 400 MHz/2400 MFLOPS. Some models support multiplemultipliers andALUs,SIMD instructions and audio processing-specific components and peripherals. TheBlackfin family of embedded digital signal processors combine the features of a DSP with those of a general use processor. As a result, these processors can run simpleoperating systems likeμCLinux, velocity andNucleus RTOS while operating on real-time data. The SHARC-based ADSP-210xx provides bothdelayed branches and non-delayed branches.[21]
NXP Semiconductors produce DSPs based onTriMediaVLIW technology, optimized for audio and video processing. In some products the DSP core is hidden as a fixed-function block into aSoC, but NXP also provides a range of flexible single core media processors. The TriMedia media processors support bothfixed-point arithmetic as well asfloating-point arithmetic, and have specific instructions to deal with complex filters and entropy coding.
CSR produces the Quatro family of SoCs that contain one or more custom Imaging DSPs optimized for processing document image data for scanner and copier applications.
Microchip Technology produces the PIC24 based dsPIC line of DSPs. Introduced in 2004, the dsPIC is designed for applications needing a true DSP as well as a truemicrocontroller, such as motor control and in power supplies. The dsPIC runs at up to 40MIPS, and has support for 16 bit fixed point MAC, bit reverse and modulo addressing, as well as DMA.
Most DSPs use fixed-point arithmetic, because in real world signal processing the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware complexity. Floating point DSPs may be invaluable in applications where a wide dynamic range is required. Product developers might also use floating point DSPs to reduce the cost and complexity of software development in exchange for more expensive hardware, since it is generally easier to implement algorithms in floating point.
Generally, DSPs are dedicated integrated circuits; however DSP functionality can also be produced by usingfield-programmable gate array chips (FPGAs).
Embedded general-purpose RISC processors are becoming increasingly DSP like in functionality. For example, theOMAP3 processors include anARM Cortex-A8 and C6000 DSP.
In Communications a new breed of DSPs offering the fusion of both DSP functions and H/W acceleration function is making its way into the mainstream. Such Modem processors includeASOCS ModemX and CEVA's XC4000.
In May 2018, Huarui-2 designed by Nanjing Research Institute of Electronics Technology ofChina Electronics Technology Group passed acceptance. With a processing speed of 0.4 TFLOPS, the chip can achieve better performance than current mainstream DSP chips.[22] The design team has begun to create Huarui-3, which has a processing speed in TFLOPS level and a support forartificial intelligence.[23]
Since the 2010s, an increasing proportion of radios designed for reception of traditional analogFM andAM short and medium wave broadcasts have replaced much of the analog tuning circuitry in older designs with DSP-based digitalICs which perform the bulk of the processing and decoding in the digital domain. An example of such an IC is theSilicon Labs/Skyworks Si4831/35 series which supports both FM and AM decoding within a single chip.[25][26]
Many such ICs (including the Si4831/35 above) are suitable for use with- and designed for- externally traditional, mechanically-tuned designs.[26][24] Compared to traditional "true" analog circuitry, these may exhibit noticeable tuning and audio idiosyncracies (e.g. tuning jumping in discrete "steps" rather than continuously),[27] particularly with older DSP-based designs.
{{cite web}}: CS1 maint: archived copy as title (link)This simple, easy-to-use FM/AM radio features a Universal Design for easy viewing and a new digital tuner for easy and stable tuning. [..] Frequency Range FM 87 - 108MHz (50kHz step) AM 520 - 1730kHz (9/10kHz step) [Discrete tuning steps indicate use of DSP-based technology]
Si4831/35 is digital in nature—an MCU and a DSP are integrated inside the chip.
Several years ago [SiLabs] altered the entire radio landscape with one little chip. Indeed, most new digital shortwave/AM/FM radios on the market use a SiLabs (or other manufacturer's) DSP chip as the centerpiece of their receiver architecture [..] but [does] using a digital chip [with a mechanical analog tuned radio] make sense? SiLabs and [others] believe the [it does] [..] Tuning: not quite an analog radio [..] stations and static pass by in comparatively coarse 5 kHz chunks [amongst other listed idiosyncracies]
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