Passbandmodulation
Analog modulation
AM SM SSB Angle modulation FM PM QAM
Digital modulation
ASK APSK CPM FSK MFSK MSK OOK PPM PSK QAM SC-FDE TCM TC-PAM WDM
Hierarchical modulation
QAM WDM
Spread spectrum
CSS DSSS FHSS THSS
See also
Capacity-approaching codes Demodulation Line coding Modem AnM PoM PAM PCM PDM PWM ΔΣM OFDM FDM Multiplexing
v t e

Delta-sigma (ΔΣ; orsigma-delta,ΣΔ) modulation is anoversampling method for encodingsignals into lowbit depthdigital signals at a very highsample-frequency as part of the process of delta-sigmaanalog-to-digital converters (ADCs) anddigital-to-analog converters (DACs). Delta-sigma modulation achieves highquality by utilizing anegative feedback loop during quantization to the lower bit depth that continuously correctsquantization errors and moves quantization noise to higher frequencies well above the original signal'sbandwidth. Subsequentlow-pass filtering fordemodulation easily removes this high frequency noise andtime averages to achieve high accuracy in amplitude, which can be ultimately encoded aspulse-code modulation (PCM).

Both ADCs and DACs can employ delta-sigma modulation. A delta-sigma ADC (e.g. Figure 1 top) encodes ananalog signal using high-frequency delta-sigma modulation and then applies adigital filter to demodulate it to a high-bit digital output at a lower sampling-frequency. A delta-sigma DAC (e.g. Figure 1 bottom) encodes a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal that may then be mapped tovoltages and smoothed with an analog filter for demodulation. In both cases, the temporary use of a low bit depth signal at a higher sampling frequency simplifies circuit design and takes advantage of the efficiency and high accuracy in time ofdigital electronics.

Primarily because of its cost efficiency and reduced circuit complexity, this technique has found increasing use in modern electronic components such as DACs, ADCs,frequency synthesizers,switched-mode power supplies andmotor controllers.^[1] The coarsely-quantized output of a delta-sigma ADC is occasionally used directly in signal processing or as a representation for signal storage (e.g.,Super Audio CD stores the raw output of a 1-bit delta-sigma modulator).

While this article focuses onsynchronous modulation, which requires a precise clock for quantization,asynchronous delta-sigma modulation instead runs without a clock.

When transmitting an analog signal directly, allnoise in the system and transmission is added to the analog signal, reducing its quality.Digitizing it enables noise-free transmission, storage, and processing. There are many methods of digitization.

In Nyquist-rate ADCs, an analog signal issampled at a relatively low sampling frequency just above itsNyquist rate (twice the signal's highest frequency) andquantized by a multi-level quantizer to produce a multi-bitdigital signal. Such higher-bit methods seek accuracy in amplitude directly, but require extremely precise components and so may suffer from poor linearity.

Oversampling converters instead produce a lowerbit depth result at a much higher sampling frequency. This can achieve comparable quality by taking advantage of:

• Higher accuracy in time (afforded by high-speed digital circuits and highly accurateclocks).
• Higher linearity afforded by low-bit ADCs and DACs (for instance, a 1-bit DAC that only outputs two values of a precise high voltage and a precise low voltage is perfectly linear, in principle).
• Noise shaping: moving noise to higher frequencies above the signal of interest, so they can be easily removed withlow-pass filtering.
• Reduced steepness requirement for the analog low-passanti-aliasing filters. High-order filters with a flat passband cost more to make in the analog domain than in the digital domain.

Another key aspect given by oversampling is the frequency/resolution tradeoff. The decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the sampling rate, and hence the representable frequency range, of the signal, while increasing the sample amplitude resolution. This improvement in amplitude resolution is obtained by a sort ofaveraging of the higher-data-rate bitstream.

Delta modulation is an earlier related low-bit oversampling method that also usesnegative feedback, but only encodes thederivative of the signal (itsdelta) rather than itsamplitude. The result is a stream ofmarks and spaces representing up or down of the signal's movement, which must beintegrated to reconstruct the signal's amplitude. Delta modulation has several drawbacks. The differentiation alters the signal's spectrum by amplifying high-frequency noise, attenuating low-frequencies,^[2] and dropping theDC component. This makes its dynamic range andsignal-to-noise ratio (SNR) inversely proportional to signal frequency. Delta modulation suffers fromslope overload if signals move too fast. And it is susceptible to transmission disturbances that result incumulative error.

Delta-sigma modulation rearranges theintegrator and quantizer of a delta modulator so that the output carries information corresponding to the amplitude of the input signal instead of just its derivative.^[3] This also has the benefit of incorporating desirable noise shaping into the conversion process, to deliberately movequantization noise to frequencies higher than the signal. Since the accumulated error signal is lowpass filtered by the delta-sigma modulator's integrator before being quantized, the subsequent negative feedback of its quantized result effectively subtracts the low-frequency components of the quantization noise while leaving the higher frequency components of the noise.

In the specific case of a single-bit synchronous ΔΣ ADC, an analog voltage signal is effectively converted into a pulse frequency, or pulse density, which can be understood aspulse-density modulation (PDM). A sequence of positive and negative pulses, representing bits at a known fixed rate, is very easy to generate, transmit, and accurately regenerate at the receiver, given only that the timing and sign of the pulses can be recovered. Given such a sequence of pulses from a delta-sigma modulator, the original waveform can be reconstructed with adequate precision.

The use of PDM as a signal representation is an alternative to PCM. Alternatively, the high-frequency PDM can later bedownsampled through decimation and requantized to convert it into a multi-bit PCM code at a lower sampling frequency closer to the Nyquist rate of the frequency band of interest.

The seminal^[4] paper combining feedback with oversampling to achieve delta modulation was by F. de Jager ofPhilips Research Laboratories in 1952.^[5]

The principle of improving the resolution of a coarse quantizer by use of feedback, which is the basic principle of delta-sigma conversion, was first described in a 1954-filed patent byC. Chapin Cutler ofBell Labs.^[6] It was not named as such until a 1962 paper^[7] by Inose et al. ofUniversity of Tokyo, which came up with the idea of adding a filter in the forward path of the delta modulator.^{[8][note 1]} However, Charles B Brahm ofUnited Aircraft Corp^[9] in 1961 filed a patent "Feedback integrating system"^[10] with a feedback loop containing an integrator with multi-bit quantization shown in its Fig 1.^[2]

Wooley's "The Evolution of Oversampling Analog-to-Digital Converters"^[4] gives more history and references to relevant patents. Some avenues of variation (which may be applied in different combinations) are the modulator's order, the quantizer's bit depth, the manner of decimation, and the oversampling ratio.

Noise of the quantizer can be further shaped by replacing the quantizer itself with another ΔΣ modulator. This creates a 2^nd-order modulator, which can be rearranged in a cascaded fashion (Figure 2).^[2] This process can be repeated to increase the order even more.

While 1^st-order modulators are unconditionally stable, stability analysis must be performed for higher-order noise-feedback modulators. Alternatively, noise-feedforward configurations are always stable and have simpler analysis.^[11]§6.1

The modulator can also be classified by the bit depth of its quantizer. A quantizer that distinguishes betweenN-levels is called alog₂N bit quantizer. For example, a simple comparator has 2 levels and so is 1 bit quantizer; a 3-level quantizer is called a1.5 bit quantizer; a 4-level quantizer is a 2-bit quantizer; a 5-level quantizer is called a2.5-bit quantizer.^[12] Higher bit quantizers inherently produce less quantization noise.

One criticism of 1-bit quantization is that adequate amounts ofdither cannot be used in the feedback loop, so distortion can be heard under some conditions (more discussion atDirect Stream Digital § DSD vs. PCM).^[13][14]

Decimation is strongly associated with delta-sigma modulation, but is distinct and outside the scope of this article. The original 1962 paper didn't describe decimation. Oversampled data in the early days was sent as is. The proposal todecimate oversampled delta-sigma data usingdigital filtering before converting it intoPCM audio was made by D. J. Goodman at Bell Labs in 1969,^[15] to reduce the ΔΣ signal from its high sampling rate while increasing its bit depth. Decimation may be done in a separate chip on the receiving end of the delta-sigma bit stream, sometimes by a dedicated module inside of amicrocontroller,^[16] which is useful for interfacing with PDMMEMS microphones,^[17] though many ΔΣ ADCintegrated circuits include decimation. Some microcontrollers even incorporate both the modulator and decimator.^[18]

Decimation filters most commonly used for ΔΣ ADCs, in order of increasing complexity and quality, are:

1. Boxcar moving average filter (simple moving average orsinc-in-frequency or sinc¹ filter): This is the easiest digital filter and retains a sharp step response, but is mediocre at separating frequency bands^[19] and suffers fromintermodulation distortion. The filter can be implemented by simply counting how many samples during a larger sampling interval are high. The 1974 paper from another Bell Labs researcher, J. C. Candy, "A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters"^[20] was one of the early examples of this.
2. Cascaded integrator–comb filters: These are called sinc^N filters, equivalent to cascading the above sinc¹ filter N times and rearranging the order of operations for computational efficiency. Lower N filters are simpler, settle faster, and have less attenuation in the baseband, while higher N filters are slightly more complex and settle slower and have more droop in the passband, but better attenuate undesired high frequency noise. Compensation filters can however be applied to counteract undesired passband attenuation.^[21] Sinc^N filters are appropriate for decimating sigma delta modulation down to four times the Nyquist rate.^[22] The height of the first sideload is -13·N dB and the height of successive lobes fall off gradually, but only the areas around the nulls will alias into the low frequency band of interest; for instance when downsampling by 8, the largestaliased high frequency component may be -16 dB below the peak of the band of interest with a sinc¹ filter but -40 dB below for a sinc³ filter, and if only interested in a narrower bandwidth, even fewer high frequency components will alias into it (see Figures 7–9 of Lyons article).^[23]
3. Windowedsinc-in-time (brick-wall in frequency) filters: Although thesinc function'sinfinite support prevents it from beingrealizable in finite time, the sinc function can instead bewindowed to realizefinite impulse response filters. This approximated filter design, while maintainingalmost no attenuation of the lower-frequency band of interest, still removesalmost all undesired high-frequency noise. The downside is poor performance in the time domain (e.g.step response overshoot and ripple), higher delay (i.e. theirconvolution time is inversely proportional to their cutoff transition steepness), and higher computational requirements.^[24] They are thede facto standard forhigh fidelity digital audio converters.

Most commercial ΔΣ modulators use integrators as the loop filter, because as low-pass filters they push quantization noise up in frequency, which is useful for baseband signals. But a ΔΣ modulator's filter does not necessarily need to be a low-pass filter. If aband-pass filter is used instead, then quantization noise is moved up and down in frequency away from the filter's pass-band, so a subsequent pass-band decimation filter will result in a ΔΣ ADC with a bandpass characteristic.^[25]

When a signal is quantized, the resulting signal can be approximated by addition ofwhite noise with approximately equal intensity across the entire spectrum. In reality, the quantization noise is, of course, not independent of the signal and this dependence results inlimit cycles and is the source of idle tones and pattern noise in delta-sigma converters. However, addingdithering noise (Figure 3) reduces suchdistortion by making quantization noise more random.

ΔΣ ADCs reduce the amount of this noise in thebaseband by spreading it out and shaping it so it is mostly in higher frequencies. It can then be easily filtered out with inexpensive digital filters, without high-precision analog circuits needed by Nyquist ADCs.

Quantization noise in the baseband frequency range (fromDC to${\displaystyle 2f_0}$) may be reduced by increasing the oversampling ratio (OSR) defined by

${\displaystyle \mathrm{O}\mathrm{S}\mathrm{R}=\frac{f_s}{2f_0}=2^d}$

where${\displaystyle f_{\mathrm{s}}}$ is the sampling frequency and${\displaystyle 2f_0}$ is the Nyquist rate (the minimum sampling rate needed to avoid aliasing, which is twice the original signal's maximum frequency${\displaystyle f_0}$). Since oversampling is typically done in powers of two,${\displaystyle d}$ represents how many times OSR is doubled.

As illustrated in Figure 4, the total amount of quantization noise is the same both in a Nyquist converter (yellow + green areas) and in an oversampling converter (blue + green areas). But oversampling converters distribute that noise over a much wider frequency range. The benefit is that the total amount of noise in the frequency band of interest is dramatically smaller for oversampling converters (just the small green area), than for a Nyquist converter (yellow + green total area).

Figure 4 shows how ΔΣ modulationshapes noise to further reduce the amount of quantization noise in the baseband in exchange for increasing noise at higher frequencies (where it can be easily filtered out). The curves of higher-order ΔΣ modulators achieve even greater reduction of noise in the baseband.

These curves are derived using mathematical tools called theLaplace transform (forcontinuous-time signals, e.g. in an ADC's modulation loop) or theZ-transform (fordiscrete-time signals, e.g. in a DAC's modulation loop). These transforms are useful for converting harder math from thetime domain into simpler math in thecomplexfrequency domain of thecomplex variable${\displaystyle \text{s}=\sigma +j\omega }$ (in the Laplace domain) or${\displaystyle \text{z}=A{e}^{j\varphi }}$ (in the z-domain).

Figure 5 represents the 1^st-order ΔΣ ADC modulation loop (from Figure 1) as a continuous-timelinear time-invariant system in the Laplace domain with the equation:

$${\displaystyle [\text{in}(\text{s})-\mathrm{\Delta }\mathrm{\Sigma }\text{M}(\text{s})]\cdot \frac{1}{\text{s}}+\text{noise}(\text{s})=\mathrm{\Delta }\mathrm{\Sigma }\text{M}(\text{s}).}$$

TheLaplace transform of integration of a function of time corresponds to simply multiplication by${\displaystyle \frac{1}{\text{s}}}$ in Laplace notation. The integrator is assumed to be an ideal integrator to keep the math simple, but areal integrator (or similar filter) may have a more complicated expression.

The process of quantization is approximated as addition with a quantization error noise source. The noise is often assumed to be white and independent of the signal, though asquantization (signal processing) § Additive noise model explains that is not always a valid assumption (particularly for low-bit quantization).

Since the system and Laplace transform are linear, the total behavior of this system can be analyzed by separating how it affects the input from how it affects the noise:^[11]§6

$${\displaystyle \mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{total}}(\text{s})=\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{in}}(\text{s})+\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{noise}}(\text{s}).}$$

To understand how the system affect the input signal only, the noise is temporarily imagined to be 0:

$${\displaystyle [\text{in}(\text{s})-\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{in}}(\text{s})]\cdot \frac{1}{\text{s}}+0=\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{in}}(\text{s}),}$$

which can be rearranged to yield the followingtransfer function:

$${\displaystyle \frac{\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{in}}(\text{s})}{\text{in}(\text{s})}=\frac{\frac{1}{\text{s}}}{1+\frac{1}{\text{s}}}=\frac{1}{\text{s}+1}.}$$

This transfer function has a singlepole at${\displaystyle \text{s}=\text{-1}}$ in thecomplex plane, so it effectively acts as a 1^st-order low-pass filter on the input signal. (Note: itscutoff frequency could be adjusted as desired by including multiplication by a constant in the loop).

To understand how the system affects the noise only, the input instead is temporarily imagined to be 0:

$${\displaystyle [0-\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{noise}}(\text{s})]\cdot \frac{1}{\text{s}}+\text{noise}(\text{s})=\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{noise}}(\text{s}),}$$

which can be rearranged to yield the following transfer function:

$${\displaystyle \frac{\mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\text{noise}}(\text{s})}{\text{noise}(\text{s})}=\frac{1}{1+\frac{1}{\text{s}}}=\frac{s}{\text{s}+1}.}$$

This transfer function has a single zero at${\displaystyle \text{s}=0}$ and a single pole at${\displaystyle \text{s}=\text{-1},}$ so the system effectively acts as a high-pass filter on the noise that starts at 0 atDC, then gradually rises until it reaches the cutoff frequency, and then levels off.

The synchronous ΔΣ DAC's modulation loop (Figure 6) meanwhile is in discrete-time and so its analysis is in the z-domain. It is very similar to the above analysis in Laplace domain and produces similar curves. Note: many sources^{[11]§6.1[26][27]} also analyze a ΔΣ ADC's modulation loop in the z-domain, which implicitly treats the continuous analog input as a discrete-time signal. This may be a valid approximation provided that the input signal is already bandlimited and can be assumed to be not changing on time scales higher than the sampling rate. It is particularly appropriate when the modulator is implemented as aswitched capacitor circuit, which work by transferring charge between capacitors in clocked time steps.

Integration in discrete-time can be anaccumulator which repeatedly sums its input${\displaystyle x[n]}$ with the previous result of its summation${\displaystyle y[n]=x[n]+y[n-1].}$ This is represented in the z-domain by feeding back a summing node's output${\displaystyle y(\text{z})}$ though a 1-clock cycle delay stage (notated as${\displaystyle {\text{z}}^{\text{-1}}}$) into another input of the summing node, yielding${\displaystyle y(\text{z})=x(\text{z})+y(\text{z})\cdot {\text{z}}^{\text{-1}}}$. Its transfer function${\displaystyle \frac{1}{1-{\text{z}}^{\text{-1}}}}$ is often used to label integrators in block diagrams.

In a ΔΣ DAC, the quantizer may be called arequantizer or adigital-to-digital converter (DDC), because its input is already digital and quantized but is simply reducing from a higher bit depth to a lower bit depth digital signal. This is represented in the z-domain by another${\displaystyle {\text{z}}^{\text{-1}}}$ delay stage in series with adding quantization noise. (Note: some sources may have swapped ordering of the${\displaystyle {\text{z}}^{\text{-1}}}$ and additive noise stages.)

The modulator's z-domain equation arranged like Figure 6 is:$${\displaystyle [\text{in}(\text{z})-\mathrm{\Delta }\mathrm{\Sigma }\text{M}(\text{z})]\cdot \frac{1}{1-{\text{z}}^{\text{-1}}}\cdot {\text{z}}^{\text{-1}}+\text{noise}(\text{z})=\mathrm{\Delta }\mathrm{\Sigma }\text{M}(\text{z}),}$$which can be rearranged to express the output in terms of the input and noise:$${\displaystyle \mathrm{\Delta }\mathrm{\Sigma }\text{M}(\text{z})=\text{in}(\text{z})\cdot {\text{z}}^{\text{-1}}+\text{noise}(\text{z})\cdot (1-{\text{z}}^{\text{-1}}).}$$The input simply comes out of the system delayed by one clock cycle. The noise term's multiplication by${\displaystyle (1-{\text{z}}^{\text{-1}})}$ represents afirst difference backward filter (which has a single pole at the origin and a single zero at${\displaystyle \text{z}=1}$) and thus high-pass filters the noise.

Without getting into the mathematical details,^{[26](equations 8-11)} cascading${\displaystyle \mathrm{\Theta }}$ integrators to create an${\displaystyle {\mathrm{\Theta }}^{\text{th}}}$-order modulator results in:$${\displaystyle \mathrm{\Delta }\mathrm{\Sigma }{\text{M}}_{\mathrm{\Theta }}(\text{z})=\text{in}(\text{z})\cdot {\text{z}}^{\text{-1}}+\text{noise}(\text{z})\cdot (1-{\text{z}}^{\text{-1}}{)}^{\mathrm{\Theta }}.}$$Since thisfirst difference backwards filter is now raised to the power${\displaystyle \mathrm{\Theta }}$ it will have a steeper noise shaping curve, for improved properties of greater attenuation in the baseband, so a dramatically larger portion of the noise is above the baseband and can be easily filtered by an ideal low-pass filter.

The theoretical SNR indecibels (dB) for a sinusoid input travelling through a${\displaystyle {\mathrm{\Theta }}^{\text{th}}}$-order modulator with a${\displaystyle 2^d}$ OSR (and followed by an ideal low-pass decimation filter) can be mathematically derived to be approximately:^{[26](equations 12-21)}

$${\displaystyle {\text{SNR}}_{\text{dB}}\approx 3.01\cdot (2\cdot \mathrm{\Theta }+1)\cdot d-9.36\cdot \mathrm{\Theta }-2.76.}$$The theoreticaleffective number of bits (ENOB) resolution is thus improved by$\mathrm{\Theta }+\frac{1}{2}$ bits when doubling the OSR (incrementing${\displaystyle d}$), and by$d-\frac{3}{2}$ bits when incrementing the order. For comparison, oversampling a Nyquist ADC (without any noise shaping) only improves its ENOB by${\displaystyle \frac{1}{2}}$ bits for every doubling of the OSR,^[28] which is only1⁄3 of the ENOB growth rate of a 1^st-order ΔΣM.

These datapoints are theoretical. In practice, circuits inevitably experience other noise sources that limit resolution, making the higher-resolution cells impractical.

Delta-sigma modulation is related todelta modulation by the following steps (Figure 7):^[11]§6

1. Start with a block diagram of a delta modulator/demodulator.
2. Thelinearity property of integration,$\int a+\int b=\int (a+b)$, makes it possible to move the integrator from the demodulator to be before the summation.
3. Again, the linearity property of integration allows the two integrators to be combined and a delta-sigma modulator/demodulator block diagram is obtained.

Ifquantization werehomogeneous (e.g., if it werelinear), the above would be a sufficient derivation of their hypothetical equivalence. But because the quantizer isnot homogeneous, delta-sigma isinspired by delta modulation, but the two are distinct in operation.

From the first block diagram in Figure 7, the integrator in the feedback path can be removed if the feedback is taken directly from the input of the low-pass filter. Hence, for delta modulation of input signalv_in, the low-pass filter sees the signal

${\displaystyle \int \mathrm{Quantize}\left({\text{v}}_{\text{in}}-{\text{v}}_{{\text{feedback}}_{\mathrm{\Delta }}}\right)dt.}$

However, delta-sigma modulation of the same input signal places at the low-pass filter

${\displaystyle \mathrm{Quantize}\left(\int \left({\text{v}}_{\text{in}}-{\text{v}}_{{\text{feedback}}_{\mathrm{\Delta }\mathrm{\Sigma }}}\right)dt\right).}$

In other words, doing delta-sigma modulation instead of delta modulation has effectively swapped the ordering of the integrator and quantizer operations. The net effect is a simpler implementation that has the profound added benefit of shaping the quantization noise to be mostly in frequencies above the signals of interest. This effect becomes more dramatic with increasedoversampling, which allows for quantization noise to be somewhat programmable. On the other hand, delta modulation shapes both noise and signal equally.

Additionally, the quantizer (e.g.,comparator) used in delta modulation has a small output representing a small step up and down the quantized approximation of the input while the quantizer used in delta-sigma must take valuesoutside of the range of the input signal.

In general, delta-sigma has some advantages versus delta modulation:

• The structure is simplified as
  • only one integrator is needed,
  • the demodulator can be a simple linear filter (e.g., RC or LC filter) to reconstruct the signal, and
  • the quantizer (e.g., comparator) can have full-scale outputs.
• The quantized value is the integral of the difference signal, which
  • makes it less sensitive to the rate of change of the signal, and
  • helps capture low frequency and DC components.

Figure 8a: Schematic of simple delta-sigma converter.

Figure 8b: Simulated scope view of key voltage signals over time. Each minor vertical division is 1 μs, which corresponds to a sampling event of the 1 MHz clock.

Delta-sigma ADCs vary in complexity. The below circuit focuses on a simple 1st-order, 2-level quantization synchronous delta-sigma ADC without decimation.

To ease understanding, a simplecircuit schematic (Figure 8a) using ideal elements issimulated (Figure 8b voltages). It is functionally the same Analog-to-Digital ΔΣ modulation loop in Figure 1 (note: the 2-input inverting integrator combines the summing junction and integrator and produces a negative feedback result, and the flip-flop combines the sampled quantizer and conveniently naturally functions as a 1-bit DAC too).

The 20 kHz inputsine waves(t) is converted to a 1-bit PDM digital resultQ(t). 20 kHz is used as an example because that is considered the upperlimit of human hearing.

This circuit can be laid out on abreadboard with inexpensive discrete components (note some variations use different biasing and use simplerRC low-pass filters for integration instead ofop amps).^[29][30]

For simplicity, theD flip-flop is powered by dual supply voltages of V_DD = +1 V and V_SS = -1 V, so its binary outputQ(t) is either +1 V or -1 V.

The 2-input invertingop amp integrator combiness(t) withQ(t) to produceƐ(t):$${\displaystyle \epsilon (t)=-\frac{1}{RC}\int (s(t)+Q(t))dt.}$$The Greek letterepsilon is used becauseƐ(t) contains the accumulatederror that is repeatedly corrected by the feedback mechanism. While both its inputss(t) andQ(t) vary between -1 and 1 volts,Ɛ(t) instead only varies by a couplemillivolts about 0 V.

Because of the integrator'snegative sign, whenƐ(t) next gets sampled to produceQ(t), the +Q(t) in this integral actually representsnegative feedback from the previous clock cycle.

An idealD flip-flop samplesƐ(t) at the clock rate of 1 MHz. The scope view (Figure 8b) has a minor division equal to thesampling period of 1 μs, so every minor division corresponds to a sampling event. Since the flip-flop is assumed to be ideal, it treats any input voltage greater than 0 V as logical high and any input voltage smaller than 0 V as logical low, no matter how close it is to 0 V (ignoring issues of sample-and-hold time violations andmetastability).

Whenever a sampling event occurs:

• ifƐ(t) is above the 0 V threshold, thenQ(t) will go high (+1 V), or
• ifƐ(t) is below the 0 V threshold, thenQ(t) will go low (-1 V).

Q(t) is sent out as the resulting PDM output and also fed back to the 2-input inverting integrator.

The rightmost integrator performs digital-to-analog conversion onQ(t) to produce a demodulated analog outputr(t), which reconstructs the original sine wave input as piece-wise linear diagonal segments. Althoughr(t) appears coarse at this 50x oversampling rate,r(t) can be low-pass filtered to isolate the original signal. As the sampling rate is increased relative to the input signal's maximum frequency,r(t) will more closely approximate the original inputs(t).

It is worth noting that if no decimation ever took place, the digital representation from a 1-bit delta-sigma modulator is simply aPDM signal, which can easily be converted to analog using alow-pass filter, as simple as aresistor and capacitor.^[30]

However, in general, a delta-sigma DAC converts adiscrete time series signal ofdigital samples at a high bit depth into a low-bit-depth (often 1-bit) signal, usually at a much higher sampling rate. That delta-modulated signal can then be accurately converted into analog (since lower bit-depth DACs are easier to be highly-linear), which then goes through inexpensive low-pass filtering in the analog domain to remove the high-frequency quantization noise inherent to the delta-sigma modulation process.

As thediscrete Fourier transform anddiscrete-time Fourier transform articles explain, a periodically sampled signal inherently contains multiple higher frequency copies orimages of the signal. It is often desirable to remove these higher-frequency images prior to performing the actual delta-sigma modulation stage, in order to ease requirements on the eventual analog low-pass filter. This can be done byupsampling using an interpolation filter and is often the first step prior to performing delta-sigma modulation in DACs. Upsampling is strongly associated with delta-sigma DACs but not strictly part of the actual delta-sigma modulation stage (similar to how decimation is strongly associated with delta-sigma ADCs but not strictly part of delta-sigma modulation either), and the details are out of the scope of this article.

The modulation loop in Figure 6 in§ Noise shaping can easily be laid out with basic digital elements of a subtractor for the difference, anaccumulator for the integrator, and a lower-bitregister for the quantization, which carries over the most-significant bit(s) from the integrator to be the feedback for the next cycle.

This simple 1^st-order modulation can be improved by cascading two or more overflowing accumulators, each of which is equivalent to a 1^st-order delta-sigma modulator. The resulting multi-stage noise shaping (MASH)^[31] structure has a steeper noise shaping property, so is commonly used in digital audio. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise-shaping function, it has two more attractive properties:

• simple to implement in hardware; only common digital blocks such asaccumulators,adders, andD flip-flops are required
• unconditionally stable (there are no feedback loops outside the accumulators)

The technique was first presented in the early 1960s by professor Yasuhiko Yasuda while he was a student atthe University of Tokyo.^[32][11] The namedelta-sigma comes directly from the presence of a delta modulator and an integrator, as firstly introduced by Inose et al. in their patent^{[clarification needed]} application.^[7] That is, the name comes from integrating orsummingdifferences, which, in mathematics, are operations usually associated with Greek letterssigma anddelta respectively.

In the 1970s,Bell Labs engineers used the termssigma-delta because the precedent was to name variations on delta modulation with adjectives precedingdelta, and anAnalog Devices magazine editor justified in 1990 that the functional hierarchy issigma-delta, because it computes the integral of a difference.^[33]

Both namessigma-delta anddelta-sigma are frequently used.

Kikkert and Miller published a continuous-time variant called Asynchronous Delta Sigma Modulation (ADSM or ASDM) in 1975 which uses either aSchmitt trigger (i.e. a comparator withhysteresis) or (as the paper argues is equivalent) a comparator with fixed delay.^[34]

In the example in Figure 9, when the integral of the error exceeds its limits, the output changes state, producing apulse-width modulated (PWM) output wave.

Amplitude information is converted, without quantization noise, into time information of the output PWM.^[35] To convert this continuous time PWM to discrete time, the PWM may be sampled by a time-to-digital converter, whose limited resolution adds noise which can be shaped by feeding it back.^[36]

• Pulse-width modulation
• Continuously variable slope delta modulation
• Class-D amplifier (sometimes^[12] use delta-sigma modulation)

• Walt Kester (October 2008)."ADC Architectures III: Sigma-Delta ADC Basics"(PDF). Analog Devices. Retrieved2010-11-02.
• R. Jacob Baker (2009).CMOS Mixed-Signal Circuit Design (2nd ed.). Wiley-IEEE.ISBN 978-0-470-29026-2.
• R. Schreier; G. Temes (2005).Understanding Delta-Sigma Data Converters. Wiley.ISBN 978-0-471-46585-0.
• S. Norsworthy; R. Schreier; G. Temes (1997).Delta-Sigma Data Converters. Wiley.ISBN 978-0-7803-1045-2.
• J. Candy; G. Temes (1992).Oversampling Delta-sigma Data Converters. Wiley.ISBN 978-0-87942-285-1.
• Chen, Wei (2013).Asynchronous sigma delta modulators for data conversion(PDF) (PhD thesis).Imperial College London.doi:10.25560/23651. Retrieved2024-01-19.

• 1-bit A/D and D/A ConvertersArchived 2021-02-25 at theWayback Machine
• Sigma-delta techniques extend DAC resolution article by Tim Wescott 2004-06-23
• Tutorial on Designing Delta-Sigma Modulators: Part I andPart II by Mingliang (Michael) Liu
• Gabor Temes' Publications
• Sigma-Delta Modulation Primer Part II Contains Block diagrams, code, and simple explanations
• Example Simulink model & scripts for continuous-time sigma-delta ADC Contains example matlab code and Simulink model
• Bruce Wooley's Delta-Sigma Converter Projects
• An Introduction to Delta Sigma Converters (which covers both ADCs and DACs sigma-delta)
• Demystifying Sigma-Delta ADCs. This in-depth article covers the theory behind a Delta-Sigma analog-to-digital converter.
• One-Bit Delta Sigma D/A Conversion Part I: Theory article by Randy Yates presented at the 2004 comp.dsp conference
• MASH (Multi-stAge noise SHaping) structure with both theory and a block-level implementation of a MASH
• Continuous time sigma-delta ADC noise shaping filter circuit architectures discusses architectural trade-offs for continuous-time sigma-delta noise-shaping filters
• Delta Sigma Converters: Modulation – intuitive motivation for why a delta-sigma modulator works
• Digital accelerometer with feedback control using sigma-delta modulation
• Analog Devices Sigma-Delta ADC tutorial (interactive)

• Digital signal processing

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