 | This articleneeds additional citations forverification. Please helpimprove this article byadding citations to reliable sources. Unsourced material may be challenged and removed. Find sources: "Dataflow architecture" – news ·newspapers ·books ·scholar ·JSTOR(August 2012) (Learn how and when to remove this message) |
Dataflow architecture is adataflow-basedcomputer architecture that directly contrasts the traditionalvon Neumann architecture orcontrol flow architecture. Dataflow architectures have noprogram counter, in concept: the executability and execution of instructions is solely determined based on the availability of input arguments to the instructions,[1] so that the order of instruction execution may be hard to predict.
Although no commercially successful general-purpose computer hardware has used a dataflow architecture, it has been successfully implemented in specialized hardware such as indigital signal processing,network routing,graphics processing,telemetry, and more recently in data warehousing, andartificial intelligence (as: polymorphic dataflow[2] Convolution Engine,[3] structure-driven,[4] dataflowscheduling[5]). It is also very relevant in many software architectures today includingdatabase engine designs andparallel computing frameworks.[citation needed]
Synchronous dataflow architectures tune to match the workload presented by real-time data path applications such as wire speed packet forwarding. Dataflow architectures that are deterministic in nature enable programmers to manage complex tasks such as processorload balancing, synchronization and accesses to common resources.[6]
Meanwhile, there is a clash of terminology, since the termdataflow is used for a subarea of parallel programming: fordataflow programming.
Hardware architectures for dataflow was a major topic incomputer architecture research in the 1970s and early 1980s.Jack Dennis ofMIT pioneered the field of static dataflow architectures while the Manchester Dataflow Machine[7] and MIT Tagged Token architecture were major projects in dynamic dataflow.
The research, however, never overcame the problems related to:
Instructions and their data dependencies proved to be too fine-grained to be effectively distributed in a large network. That is, the time for the instructions and tagged results to travel through a large connection network was longer than the time to do many computations.
Maurice Wilkes wrote in 1995 that "Data flow stands apart as being the most radical of all approaches to parallelism and the one that has been least successful. ... If any practical machine based on data flow ideas and offering real power ever emerges, it will be very different from what the originators of the concept had in mind."[8]
Out-of-order execution (OOE) has become the dominant computing paradigm since the 1990s. It is a form of restricted dataflow. This paradigm introduced the idea of anexecution window. Theexecution window follows the sequential order of the von Neumann architecture, however within the window, instructions are allowed to be completed in data dependency order. This is accomplished in CPUs that dynamically tag the data dependencies of the code in the execution window. The logical complexity of dynamically keeping track of the data dependencies, restrictsOOECPUs to a small number of execution units (2-6) and limits the execution window sizes to the range of 32 to 200 instructions, much smaller than envisioned for full dataflow machines.[citation needed]
Designs that use conventional memory addresses as data dependency tags are called static dataflow machines. These machines did not allow multiple instances of the same routines to be executed simultaneously because the simple tags could not differentiate between them.
Designs that usecontent-addressable memory (CAM) are called dynamic dataflow machines. They use tags in memory to facilitate parallelism.
Normally, in the control flow architecture,compilers analyze programsource code for data dependencies between instructions in order to better organize the instruction sequences in the binary output files. The instructions are organized sequentially but the dependency information itself is not recorded in the binaries. Binaries compiled for a dataflow machine contain this dependency information.
A dataflow compiler records these dependencies by creating unique tags for each dependency instead of using variable names. By giving each dependency a unique tag, it allows the non-dependent code segments in the binary to be executedout of order and in parallel. Compiler detects the loops, break statements and various programming control syntax for data flow.
Programs are loaded into the CAM of a dynamic dataflow computer. When all of the tagged operands of an instruction become available (that is, output from previous instructions and/or user input), the instruction is marked as ready for execution by anexecution unit.
This is known asactivating orfiring the instruction. Once an instruction is completed by an execution unit, its output data is sent (with its tag) to the CAM. Any instructions that are dependent upon this particular datum (identified by its tag value) are then marked as ready for execution. In this way, subsequent instructions are executed in proper order, avoidingrace conditions. This order may differ from the sequential order envisioned by the human programmer, the programmed order.
An instruction, along with its required data operands, is transmitted to an execution unit as a packet, also called aninstruction token. Similarly, output data is transmitted back to the CAM as adata token. The packetization of instructions and results allows for parallel execution of ready instructions on a large scale.
Dataflow networks deliver the instruction tokens to the execution units and return the data tokens to the CAM. In contrast to the conventionalvon Neumann architecture, data tokens are not permanently stored in memory, rather they are transient messages that only exist when in transit to the instruction storage.
In contrast to the above, analog differential analyzers were based purely on hardware in the form of dataflow architecture, with the property that the programming and computations aren't performed by any set of instructions at all and that there usually weren't any memory based decisions made in such programs. The programming is solely based on the configuration by the physical interconnection of specialized computing elements, which basically creates a form of a passive dataflow architecture.
In July 2025, the startup Efficient Computer was reported to have built a dataflow chip called Electron E1.[9]