TheJ-11 is amicroprocessor chip set that implements thePDP-11instruction set architecture (ISA) jointly developed byDigital Equipment Corporation andIntersil. It was a high-end chip set designed to integrate the performance and features of thePDP-11/70 onto a handful of chips. It was used in thePDP-11/73, PDP-11/83 andProfessional 380.
It consisted of a data path chip[1] and a control chip[2] in ceramic leadless packages mounted on a single ceramichybriddual inline package (DIP). The control chip incorporated a control sequencer and a microcode ROM.[2] An optional separate floating-point accelerator (FPA) chip could be used, and was packaged in a standard DIP. The data path chip and control chip were fabricated by Intersil in a CMOS process while the FPA was fabricated by Digital in their "ZMOS" NMOS process.
The design originally was intended to support multiple control chips to allow implementation of additional instructions such as the Commercial Instruction Set (CIS), but no such control chips were ever offered.
Aclone of the J-11 was manufactured in theSoviet Union under thedesignation KN1831VM1 (Russian:КН1831ВМ1).[3]
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