Sunny Cove is acodename for a CPUmicroarchitecture developed byIntel, first released in September 2019. It succeeds thePalm Cove microarchitecture and is fabricated using Intel's10 nmprocess node and it is a major evolution over theSkylake microarchitecture which launched in 2015.^[1] The microarchitecture is implemented in 10th-generationIntel Core processors for mobile (codenamedIce Lake) and third generationXeon scalable server processors (codenamedIce Lake-SP). 10th-generation Intel Core mobile processors were released in September 2019, while the Xeon server processors were released on April 6, 2021.^[2]

There are no desktop products featuring Sunny Cove. However, a variant namedCypress Cove is used for the 11th-generation Intel Core desktop processors (codenamedRocket Lake). Cypress Cove is a version of the Sunny Cove microarchitecture backported to Intel's 14 nmprocess node.^[3]

The direct successor to the Sunny Cove microarchitecture is theWillow Cove microarchitecture, which powers the 11th-generation Intel Core mobile processors.^[4]

Sunny Cove was designed by Intel Israel's processor design team inHaifa, Israel.^[5][6]

Intel released details of Ice Lake and its microarchitecture, Sunny Cove, during Intel Architecture Day in December 2018, stating that the Sunny Cove cores would be focusing on single-thread performance, new instructions, and scalability improvements. Intel stated that the performance improvements would be achieved by making the core "deeper, wider, and smarter".^[7]

Sunny Cove features a 50% increase in the size of L1 data cache, a larger L2 cache dependent on product size, larger μOP cache, and larger second-levelTLB. The core has also increased in width, by increasing execution ports from eight to ten and by doubling the L1 store bandwidth. Allocation width has also increased from four to five. The5-level paging scheme supports a linear address space up to 57 bits and a physical address space up to 52 bits, increasing the virtual memory space to 128 petabytes, up from 256 terabytes, and the addressable physical memory to 4 petabytes, up from 64 terabytes.^[8][7]

• On average 18% increase inIPC in comparison to 2015Skylake running at the same frequency and memory configuration^[9][10]
• Increase L1 data cache: 48 kiB (from 32 kiB)
• L2 cache: 512 kiB^[11]
• Larger micro-instruction cache (2304 entries, up from 1536)
• Largerre-order buffer (352, up from 224 entries)
• Dynamic Tuning 2.0 which allows the CPU to stay at turbo frequencies for longer^[12][13]
• Hardware acceleration for SHA operations (Secure Hash Algorithms)
• NewAVX-512 instruction subsets:
  • VPOPCNTDQ
  • VBMI2
  • BITALG
  • VPCLMULQDQ
  • GFNI
  • VAES
  • VNNI
• Wider decoder (from skylake's 3 simple + 1 complex 4 way decoding to Sunny cove's 4 simple + 1 complex 5 wide decoder)
• 1.6x larger ROB (352, up from 224 entries)
  • Scheduler
    • 1.65x larger scheduler (160-entry, up from 97 entries)
    • Larger dispatch (10-way, up from 8-way)
  • 1.55x larger integer register file (280-entry, up from 180)
  • 1.33x larger vector register file (224-entry, up from 168)
  • Distributed scheduling queues (4 scheduling queues, up from 2)
• IntelDeep Learning Boost, used formachine learning/artificial intelligenceinference acceleration^[14][13]

Cypress Cove

Cypress Cove die from an i5-11400
General information
Launched	March 30, 2021; 4 years ago (2021-03-30)
Designed by	Intel
Common manufacturer	Intel
Cache
L1cache	80 KB per core: 32 KB instructions 48 KB data
L2 cache	512 KB per core
L3 cache	2 MB per core
Architecture and classification
Technology node	Intel14 nmFinFET process
Instruction set	x86,x86-64
Extensions	MMX,SSE,SSE2,SSE3,SSSE3,SSE4,SSE4.1,SSE4.2 AVX,AVX2,AVX-512,FMA3 AES,CLMUL,RDRAND,SHA,TXT VT-d,VT-x
Products, models, variants
Product code name	Rocket Lake
History
Predecessor	Skylake
Successor	Golden Cove

Cypress Cove is a CPU microarchitecture based on the Sunny Cove microarchitecture designed for 10 nm, backported to 14 nm. It succeeds theSkylake microarchitecture, and is manufactured using Intel's 14 nmprocess node. Cypress Cove is identical to Sunny Cove, aside from a number of improvements and other changes.^[15] Notably the L1 data cache latency has been reduced from five cycles that is on Sunny Cove to just three cycles on Cypress Cove by change from 8 way associativity on Sunny Cove to 12 way associativity On Cypress Cove. Intel claims an increase of 19% in IPC in Cypress Cove–based Rocket Lake processors compared toComet Lake.^[15][16]

Cypress Cove is implemented on 11th Gen Intel Core desktop processors (codenamedRocket Lake). Rocket Lake and its underlying microarchitecture were first described in November 2020,^[3] and was later released on March 30, 2021.^[17][18]

SGX is removed from Rocket Lake.

Sunny Cove powers the 10th generation ofIntel Core mobile processors (codenamedIce Lake) and the third generation ofXeon Scalable server processors (codenamedIce Lake-SP). Cypress Cove is implemented on 11th-generation Intel Core desktop processors (codenamedRocket Lake).

• X86 microarchitectures
• Intel
• Intel microarchitectures

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