| Cray X-MP | |
|---|---|
 The CERN Cray X-MP/48 displayed at theEPFL inSwitzerland. | |
| Design | |
| Manufacturer | Cray Research |
| Designer | Steve Chen |
| Release date | 1982 (1982) |
| Price | $15 million[1] |
| Casing | |
| Dimensions | 2.62 m (8.6 ft) x 1.96 m (6.4 ft) |
| Weight | 5.12 t (11,300 lb)[2] |
| Power | 345 kW[3] |
| System | |
| Front-end | Most minicomputers of the time |
| Operating system | COS, UNICOS |
| CPU | 4x Vector processor 64 bits @ 105 - 117 MHz |
| Memory | 128megabytes |
| Storage | 38.4gigabytes (32 disks) |
| MIPS | 400 MIPS (4 CPU) |
| FLOPS | 800MFLOPS (4 CPU) |
| Predecessor | Cray-1 |
| Successor | Cray Y-MP |
TheCray X-MP was asupercomputer designed, built and sold byCray Research. It was announced in 1982 as the "cleaned up" successor to the 1975Cray-1, and was the world's fastest computer from 1983 to 1985 with a quad-processor system performance of 800MFLOPS.[4] The principal designer wasSteve Chen.
The X-MP's main improvement over the Cray-1 was that it was a shared-memoryparallelvector processor, the first such computer from Cray Research. It housed up to four CPUs in a mainframe that was nearly identical in outside appearance to the Cray-1.
The X-MP CPU had a faster 9.5 nanosecond clock cycle (105 MHz), compared to 12.5 ns for the Cray-1A. It was built frombipolargate-arrayintegrated circuits containing 16emitter-coupled logicgates each. The CPU was very similar to the Cray-1 CPU in architecture, but had better memory bandwidth (with two read ports and one write port to the main memory instead of only one read/write port) and improved chaining support. Each CPU had a theoretical peak performance of 200 MFLOPS.[5]
The X-MP initially supported 2 million 64-bitwords (16 MB) of main memory in 16 banks, respectively.[citation needed] The main memory was built from 4 Kbit bipolar SRAM ICs.[citation needed] CMOS memory versions of the Cray-1M were renamed Cray X-MP/1s. This configuration was first used for Cray Research's UNIX port.
In 1984, improved models of the X-MP were announced, consisting of one, two, and four-processor systems with 4 and 8 million word configurations. The top-end system was the X-MP/48, which contained four CPUs with a theoretical peak system performance of over 800 MFLOPS and 8 million words of memory.[5] The CPUs in these models introduced vectorgather/scatter memory reference instructions to the product line. The amount of main memory supported was increased to a maximum of 16 million words, depending on the model. The main memory was built from bipolar or MOS SRAM ICs, depending on the model.
The system initially ran the proprietaryCray Operating System (COS) and was object-code compatible with the Cray-1. AUNIX System V derivative initially named CX-OS and finally renamedUNICOS ran through a guestoperating system facility. UNICOS became the main OS from 1986 onwards. TheDOE ran theCray Time Sharing System and theNLTSS operating systems instead. See the Software section for theCray-1 for a more detailed elaboration of software (language compiler, assembler, operating systems, and applications) as X-MPs and Cray-1s were mostly compatible.
Cray Research announced the X-MP Extended Architecture series in 1986. The EA series CPU had an 8.5 ns clock cycle (117 MHz), and was built frommacrocell array and gate array ICs. The EA series extended the width of the A and B registers to 32 bits and performed 32-bit address arithmetic, increasing the amount of memory theoretically addressable to 2 billion words. The largest configuration produced was 64 million words of MOS SRAM in 64 banks. For compatibility with existing software written for the Cray-1 and older X-MP models, 24-bit addressing was also supported. Each EA series CPU's peak performance was 234 MFLOPS. For a four-processor system, the peak performance was 942 MFLOPS.[citation needed]
TheInput/Output (I/O) subsystem could have two to four I/O processors with a total of 2 to 32 disk storage units. The DD-39 and DD-49 hard drives made byIbis with a raw transfer rate of 13.3 MB/s each stored 1200 megabyte (blocked and formatted) with 5.9 MB/s and 9.8 MB/s transfer rates (unstriped), respectively. Optionalsolid-state drives were available with 256, 512 or 1024 MB capacities with transfer rates of 100 to 1,000 MB/s per channel. Up to 38 gigabytes of data storage was possible.[5][6]
Formagnetic tape I/O, the system could interface withIBM 3420 and3480 tape units directly without a lot of CPU processing.[6]
A 1984 X-MP/48 cost aboutUS$15 million plus the cost ofdisks. In 1985Bell Labs purchased a Cray X-MP/24 for $10.5 million along with eight DD-49 1.2 GB drives for an additional $1 million. They received $1.5 million of trade-in credit for their Cray-1.[7]
TheCray-2, a completely new design, was introduced in 1985. A very different compact four-processor design with from 64 MW (megaword) to 512 MW (512 MB to 4 GB) of main memory, it was specified to 500 MFLOPS but was slower than the X-MP on certain calculations due to its high memory latency.
TheCray Y-MP upgrade of the X-MP series was announced in 1988; it also had a new design, replacing the 16-gate ECLgate arrays with a more compactVLSI gate array with larger circuit boards. It was a major improvement of the X-MP supporting up to eight processors.
Media related toCray-XMP48 at Wikimedia Commons| Records | ||
|---|---|---|
| Preceded by Cray-1 136 megaflops | World's most powerful supercomputer 1983–1985 | Succeeded by Cray-2 1.95 gigaflops (peak) |
Cray computers | ||
|---|---|---|
| Cray Research |  | |
| Cray Computer Corp. | ||
| Cray Research Superservers | ||
| Cray Inc. | ||
