Computational RAM (C-RAM) israndom-access memory withprocessing elements integrated on the same chip. This enables C-RAM to be used as aSIMD computer. It also can be used to more efficiently use memory bandwidth within a memory chip. The general technique of doing computations in memory is called Processing-In-Memory (PIM).

The most influential implementations of computational RAM came fromThe Berkeley IRAM Project. Vector IRAM (V-IRAM) combinesDRAM with avector processor integrated on the same chip.^[1]

Reconfigurable Architecture DRAM (RADram) isDRAM withreconfigurable computingFPGA logic elements integrated on the same chip.^[2]SimpleScalar simulations show that RADram (in a system with a conventional processor) can give orders of magnitude better performance on some problems than traditional DRAM (in a system with the same processor).

Someembarrassingly parallel computational problems are already limited by thevon Neumann bottleneck between the CPU and the DRAM.Some researchers expect that, for the same total cost, a machine built from computational RAM will run orders of magnitude faster than a traditional general-purpose computer on these kinds of problems.^[3]

As of 2011, the "DRAM process" (few layers; optimized for high capacitance) and the "CPU process" (optimized for high frequency; typically twice as manyBEOL layers as DRAM; since each additional layer reduces yield and increases manufacturing cost, such chips are relatively expensive per square millimeter compared to DRAM) is distinct enough that there are three approaches to computational RAM:

• starting with a CPU-optimized process and a device that uses much embedded SRAM, add an additional process step (making it even more expensive per square millimeter) to allow replacing the embedded SRAM with embedded DRAM (eDRAM), giving ≈3x area savings on the SRAM areas (and so lowering net cost per chip).
• starting with a system with a separate CPU chip and DRAM chip(s), add small amounts of "coprocessor" computational ability to the DRAM, working within the limits of the DRAM process and adding only small amounts of area to the DRAM, to do things that would otherwise be slowed down by the narrow bottleneck between CPU and DRAM: zero-fill selected areas of memory, copy large blocks of data from one location to another, find where (if anywhere) a given byte occurs in some block of data, etc. The resulting system—the unchanged CPU chip, and "smart DRAM" chip(s)—is at least as fast as the original system, and potentially slightly lower in cost. The cost of the small amount of extra area is expected to be more than paid back in savings in expensive test time, since there is now enough computational capability on a "smart DRAM" for a wafer full of DRAM to do most testing internally in parallel, rather than the traditional approach of fully testing one DRAM chip at a time with an expensive externalautomatic test equipment.^[1]
• starting with a DRAM-optimized process, tweak the process to make it slightly more like the "CPU process", and build a (relatively low-frequency, but low-power and very high bandwidth) general-purpose CPU within the limits of that process.

Some CPUs designed to be built on a DRAM process technology (rather than a "CPU" or "logic" process technology specifically optimized for CPUs) includeThe Berkeley IRAM Project, TOMI Technology^[4][5]and theAT&T DSP1.

Because a memory bus to off-chip memory has many times the capacitance of an on-chip memory bus, a system with separate DRAM and CPU chips can have several times theenergy consumption of an IRAM system with the samecomputer performance.^[1]

Because computational DRAM is expected to run hotter than traditional DRAM,and increased chip temperatures result in faster charge leakage from the DRAM storage cells,computational DRAM is expected to require more frequentDRAM refresh.^[2]

This sectionrelies excessively onreferences toprimary sources. Please improve this section by addingsecondary or tertiary sources. Find sources: "Computational RAM" – news ·newspapers ·books ·scholar ·JSTOR(August 2012) (Learn how and when to remove this message)

This sectionneeds additional citations forverification. Please helpimprove this article byadding citations to reliable sources in this section. Unsourced material may be challenged and removed. Find sources: "Computational RAM" – news ·newspapers ·books ·scholar ·JSTOR(August 2012) (Learn how and when to remove this message)

Aprocessor-in-/near-memory (PINM) refers to acomputer processor (CPU) tightly coupled tomemory, generally on the samesilicon chip.

The chief goal of merging the processing and memory components in this way is to reducememory latency and increasebandwidth. Alternatively reducing the distance that data needs to be moved reduces the power requirements of a system.^[6] Much of the complexity (and hencepower consumption) in current processors stems from strategies to deal with avoiding memory stalls.

In the 1980s, a tiny CPU that executedFORTH was fabricated into aDRAM chip to improve PUSH and POP.FORTH is astack-oriented programming language and this improved its efficiency.

Thetransputer also had large on chip memory given that it was made in the early 1980s making it essentially a processor-in-memory.

Notable PIM projects include theBerkeley IRAM project (IRAM) at theUniversity of California, Berkeley^[7] project and theUniversity of Notre Dame PIM^[8] effort.

DRAM-based near-memory and in-memory designs can be categorized into four groups:

• DIMM-level approaches place the processing units near memory chips. These approaches require minimal/no change in the data layout(e.g., Chameleon,^[9] and RecNMP^[10] ).
• Logic-layer-level approaches embed processing units in the logic layer of 3D stack memories and can benefit from the high bandwidth of 3D stack memories (e.g., TOP_PIM^[11])
• Bank-level approaches place processing units inside the memory layers, near each bank. UPMEM and Samsung's PIM^[12] are examples of these approaches
• Subarray-level approaches process data inside each subarray. The Subarray-level approaches provide the highest access parallelism but often perform only simple operations, such as bitwise operations on an entire memory row (e.g., DRISA^[13]) or sequential processing of the memory row using a single-world ALU (e.g., Fulcrum^[14])

• Computing with memory
• SyNAPSE also combines processing and memory in one chip.
• In-memory processing

• Duncan Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie, "Computational RAM: Implementing Processors in Memory",IEEE Design and Test of Computers, vol. 16, no. 1, pp. 32–41, Jan–Mar 1999.doi:10.1109/54.748803.

• Computer memory
• Computer architecture

• Webarchive template wayback links
• All articles with dead external links
• Articles with dead external links from August 2017
• Articles with permanently dead external links
• CS1 maint: archived copy as title
• Articles with short description
• Short description matches Wikidata
• Articles lacking reliable references from August 2012
• All articles lacking reliable references
• Articles needing additional references from August 2012
• All articles needing additional references