Aninstruction set architecture (ISA) is an abstract model of acomputer, also referred to ascomputer architecture. A realization of an ISA is called animplementation. An ISA permits multiple implementations that may vary inperformance, physical size, and monetary cost (among other things); because the ISA serves as theinterface betweensoftware andhardware, software that has been written or compiled for an ISA can run on different implementations of the same ISA. This has enabledbinary compatibility between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions incomputing today.

An ISA defines everything amachine languageprogrammer needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supporteddata types, what state there is (such as themain memory andregisters) and their semantics (such as thememory consistency andaddressing modes), theinstruction set (the set ofmachine instructions that comprises a computer's machine language), and theinput/output model.

In the early decades of computing, there were computers that usedbinary,decimal^[1] and eventernary.^[2][3] Contemporary computers are almost exclusively binary.

Characters are encoded as strings of bits or digits, using a wide variety of character sets; even within a single manufacturer there were character set differences.

Integers are encoded with a variety ofrepresentations, includingSign-magnitude,Ones' complement,Two's complement,Offset binary,Nines' complement andTen's complement.

Similarly, floating point numbers are encoded with a variety of representations for the sign,exponent andmantissa. In contemporary machinesIBM hexadecimal floating-point andIEEE 754 floating point have largely supplanted older formats.

Addresses are typically unsigned integers generated from a combination of fields in an instruction, data from registers and data from storage; the details vary depending on the architecture.

Computer architectures are often described asn-bit architectures. In the first3⁄4 of the 20th century,n is often12,18,24, 30,36,48 or60. In the last1⁄3 of the 20th century,n is often 8, 16, or 32, and in the 21st century,n is often 16, 32 or 64, but other sizes have been used (including 6,39,128). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in theinstruction set, but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are theZ80,MC68000, and theIBM System/360. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a32-bit architecture with a16-bit implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as theIBM System/360 Model 30, have smaller internal data paths, while others, such as the360/195, have larger internal data paths.

The external databus width is not used to determine the width of the architecture; theNS32008, NS32016 and NS32032 were basically the same 32-bit chip with different external data buses. IBM'sPowerPC 604 has a 64-bit bus but only 32-bit registers. The System/360 processors, and some early 32-bit microprocessors such as theMotorola 68000, have 24-bit addresses.

The bit width of instructions in an architecture is not necessarily the bit width of the architecture. For example, instructions in System/360, thePDP-11 architecture, theVAX architecture, and thex86 architecture are variable-length. Initial versions ofSuperH had fixed-length 16-bit instructions in spite of having a 32-bit architecture, while later versions had both 16-bit and 32-bit instructions.

In the first3⁄4 of the 20th century, word oriented decimal computers typically had 10 digit^[4][5][6] words with a separate sign,^[a] using all ten digits in integers and using two digits for exponents^[7][5] in floating point numbers.

An architecture may use "big" or "little" endianness, or both, or be configurable to use either. Little-endian processors orderbytes in memory with the least significant byte of a multi-byte value in the lowest-numbered memory location. Big-endian architectures instead arrange bytes with the most significant byte at the lowest-numbered address. The x86 architecture as well as several8-bit architectures are little-endian. MostRISC architectures (SPARC, Power, PowerPC, MIPS) were originally big-endian (ARM was little-endian), but many (including ARM) are now configurable as either.

Endiannessonly applies to processors that allow individual addressing of units of data (such asbytes) that aresmaller than some of the data formats.

In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on theIBM System/370, byte 0 is the opcode but when byte 0 is a B2₁₆ then byte 1 selects a specific instruction, e.g., B205₁₆ is store clock (STCK). On some instruction set architectures, one or moreopcode prefixes are used to alter the subsequent opcode or expand the number of opcodes.

Architectures typically allow instructions to include some combination of operandaddressing modes:

Direct

The instruction specifies a complete address

Immediate

The instruction specifies a value rather than an address

Indexed

The instruction specifies a register to use as an index. In some architecture the index is scaled by the operand length.

Indirect

The instruction specifies the location of a pointer word that describes the operand, possibly involving multiple levels of indexing and indirection

Truncated

The instruction specifies the low order bits and a register provides the high order bits.

Base-displacement

The instruction specifies a displacement from an address in a register

autoincrement/autodecrement

A register used for indexing, or a pointer word used by indirect addressing, is incremented or decremented by 1, an operand size or an explicit delta

Vector processors have offeredadditional modes unique to element-based operations.

The number of operands is one of the factors that may give an indication about the performance of the instruction set.A three-operand architecture (2-in, 1-out) will allow

A := B + C

to be computed in one instruction

ADD B, C, A

A two-operand architecture (1-in, 1-in-and-out) will allow

A := A + B

to be computed in one instruction

ADD B, A

but requires that

A := B + C

be done in two instructions

MOVE B, AADD C, A

As can be seen in the table below some instructions sets keep to a very simple fixed encoding length, and other have variable-length. Usually it isRISC architectures that have fixed encoding length andCISC architectures that have variable length, but not always.

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The table below compares basic information about instruction set architectures.

Notes:

• Usually the number of registers is apower of two, e.g. 8, 16, 32. In some cases a hardwired-to-zero pseudo-register is included, as "part" ofregister files of architectures, mostly to simplify indexing modes. The column "Registers" only counts the integer "registers" usable by general instructions at any moment. Architectures always include special-purpose registers such as the program counter (PC). Those are not counted unless mentioned. Note that some architectures, such as SPARC, haveregister windows; for those architectures, the count indicates how many registers are available within a register window. Also, non-architected registers forregister renaming are not counted.
• In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "load–store", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.
• In the "Endianness" column, "Bi" means that the endianness is configurable.

• Central processing unit (CPU)
• Processor design
• Comparison of CPU microarchitectures
• Instruction set architecture
• Microprocessor
• Benchmark (computing)

• Instruction set architectures
• Computer architecture
• Computing comparisons

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