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CUDA

From Wikipedia, the free encyclopedia
Parallel computing platform and programming model
For other uses, seeCUDA (disambiguation).
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CUDA
Original authorsIan Buck
John Nickolls
DeveloperNvidia
Initial releaseFebruary 16, 2007; 18 years ago (2007-02-16)[1]
Stable release
13.0.0[2]Edit this on Wikidata / 6 August 2025; 2 months ago (6 August 2025)
Written inC
Operating systemWindows,Linux
PlatformSupported GPUs
TypeGPGPU
LicenseProprietary
Websitedeveloper.nvidia.com/cuda-zoneEdit this at Wikidata

CUDA (Compute Unified Device Architecture) is a proprietary[3]parallel computing platform andapplication programming interface (API) that allows software to use certain types ofgraphics processing units (GPUs) for accelerated general-purpose processing, significantly broadening their utility in scientific andhigh-performance computing. CUDA was created byNvidia starting in 2004 and was officially released in 2007.[4] When it was first introduced, the name was an acronym forCompute Unified Device Architecture,[5] but Nvidia laterdropped the common use of the acronym and now rarely expands it.[6]

CUDA is both a software layer that manages data, giving direct access to the GPU and CPU as necessary, and a library of APIs that enable parallel computation for various needs.[7][8] In addition todrivers and runtime kernels, the CUDA platform includes compilers, libraries and developer tools to help programmers accelerate their applications.

CUDA is written inC but is designed to work with a wide array of otherprogramming languages includingC++,Fortran,Python andJulia. This accessibility makes it easier for specialists in parallel programming to use GPU resources, in contrast to prior APIs likeDirect3D andOpenGL, which require advanced skills in graphics programming.[9] CUDA-powered GPUs also support programming frameworks such asOpenMP,OpenACC andOpenCL.[10][7]

Background

[edit]
Further information:Graphics processing unit

The graphics processing unit (GPU), as a specialized computer processor, addresses the demands ofreal-time high-resolution3D graphics compute-intensive tasks. By 2012, GPUs had evolved into highly parallelmulti-core systems allowing efficient manipulation of large blocks of data. This design is more effective than general-purposecentral processing unit (CPUs) foralgorithms in situations where processing large blocks of data is done in parallel, such as:

The origins of CUDA trace back to the early 2000s, whenIan Buck, a computer science Ph.D. student atStanford University, began experimenting with using GPUs for purposes beyond rendering graphics. Buck had first become interested in GPUs during his undergraduate studies atPrinceton University, initially throughvideo gaming. After graduation, he interned at Nvidia, gaining deeper exposure to GPU architecture. At Stanford, he built an 8K gaming rig using 32GeForce graphics cards, originally to push the limits of graphics performance in games likeQuake andDoom. However, his interests shifted toward exploring the potential of GPUs forgeneral-purpose parallel computing.[11]

To that end, Buck developed Brook, a programming language designed to enable general-purpose computing on GPUs. His work attracted support from both Nvidia and theDefense Advanced Research Projects Agency (DARPA). In 2004, Nvidia hired Buck and paired him with John Nickolls, the company's director of architecture for GPU computing. Together, they began transforming Brook into what would become CUDA.[11] CUDA was officially released by Nvidia in 2007.

Under the leadership of Nvidia CEOJensen Huang, CUDA became central to the company's strategy of positioning GPUs as versatile hardware for scientific applications. By 2015, CUDA's development increasingly focused on acceleratingmachine learning andartificial neural network workloads.[12]

Ontology

[edit]

The following table offers a non-exact description for theontology of the CUDA framework.

The ontology of CUDA framework
memory
(hardware)		memory (code, orvariable scoping)computation
(hardware)		computation
(code syntax)		computation
(code semantics)
RAMnon-CUDA variableshostprogramoneroutine call
VRAM,
GPU L2 cache		global, const, texturedevicegridsimultaneous call of the samesubroutine on many processors
GPU L1 cachelocal, sharedSM ("streaming multiprocessor")blockindividual subroutine call
warp = 32 threadsSIMD instructions
GPU L0 cache,
register		thread (aka. "SP", "streaming processor", "cuda core", but these names are now deprecated)analogous to individual scalar ops within a vector op

Programming abilities

[edit]
Example of CUDA processing flow
  1. Copy data from main memory to GPU memory
  2. CPU initiates the GPUcompute kernel
  3. GPU's CUDA cores execute the kernel in parallel
  4. Copy the resulting data from GPU memory to main memory

The CUDA platform is accessible to software developers through CUDA-accelerated libraries,compiler directives such asOpenACC, and extensions to industry-standard programming languages includingC,C++,Fortran andPython. C/C++ programmers can use 'CUDA C/C++', compiled toPTX withnvcc (Nvidia'sLLVM-based C/C++ compiler)[13] or by clang itself.[14] Fortran programmers can use 'CUDA Fortran', compiled with the PGI CUDA Fortran compiler fromThe Portland Group.[needs update] Python programmers can use the cuNumeric library to accelerate applications on Nvidia GPUs.

In addition to libraries, compiler directives, CUDA C/C++ and CUDA Fortran, the CUDA platform supports other computational interfaces, including theKhronos Group'sOpenCL,[15] Microsoft'sDirectCompute,OpenGL Compute Shader andC++ AMP.[16] Third party wrappers are also available forPython,Perl, Fortran,Java,Ruby,Lua,Common Lisp,Haskell,R,MATLAB,IDL,Julia, and native support inMathematica.

In thecomputer game industry, GPUs are used for graphics rendering, and forgame physics calculations (physical effects such as debris, smoke, fire, fluids); examples includePhysX andBullet. CUDA has also been used to accelerate non-graphical applications incomputational biology,cryptography and other fields by anorder of magnitude or more.[17][18][19][20][21]

CUDA provides both a low levelAPI (CUDADriver API, non single-source) and a higher level API (CUDARuntime API, single-source). The initial CUDASDK was made public on 15 February 2007, forMicrosoft Windows andLinux.Mac OS X support was later added in version 2.0,[22] which supersedes the beta released February 14, 2008.[23] CUDA works with all Nvidia GPUs from the G8x series onwards, includingGeForce,Quadro and theTesla line. CUDA is compatible with most standard operating systems.

CUDA 8.0 comes with the following libraries (for compilation & runtime, in alphabetical order):

  • cuBLAS – CUDA Basic Linear Algebra Subroutines library
  • CUDART – CUDA Runtime library
  • cuFFT – CUDA Fast Fourier Transform library
  • cuRAND – CUDA Random Number Generation library
  • cuSOLVER – CUDA based collection of dense and sparse direct solvers
  • cuSPARSE – CUDA Sparse Matrix library
  • NPP – NVIDIA Performance Primitives library
  • nvGRAPH – NVIDIA Graph Analytics library
  • NVML – NVIDIA Management Library
  • NVRTC – NVIDIA Runtime Compilation library for CUDA C++

CUDA 8.0 comes with these other software components:

  • nView – NVIDIA nView Desktop Management Software
  • NVWMI – NVIDIA Enterprise Management Toolkit
  • GameWorksPhysX – is a multi-platform game physics engine

CUDA 9.0–9.2 comes with these other components:

  • CUTLASS 1.0 – custom linear algebra algorithms,
  • NVIDIA Video Decoder was deprecated in CUDA 9.2; it is now available in NVIDIA Video Codec SDK

CUDA 10 comes with these other components:

  • nvJPEG – Hybrid (CPU and GPU) JPEG processing

CUDA 11.0–11.8 comes with these other components:[24][25][26][27]

  • CUB is new one of more supported C++ libraries
  • MIG multi instance GPU support
  • nvJPEG2000 –JPEG 2000 encoder and decoder

Advantages

[edit]

CUDA has several advantages over traditional general-purpose computation on GPUs (GPGPU) using graphics APIs:

  • Scattered reads – code can read from arbitrary addresses in memory.
  • Unified virtual memory (CUDA 4.0 and above)
  • Unified memory (CUDA 6.0 and above)
  • Shared memory – CUDA exposes a fast shared memory region that can be shared among threads. This can be used as a user-managed cache, enabling higher bandwidth than is possible using texture lookups.[28]
  • Faster downloads and readbacks to and from the GPU
  • Full support for integer and bitwise operations, including integer texture lookups

Limitations

[edit]
  • Whether for the host computer or the GPU device, all CUDA source code is now processed according to C++ syntax rules.[29] This was not always the case. Earlier versions of CUDA were based on C syntax rules.[30] As with the more general case of compiling C code with a C++ compiler, it is therefore possible that old C-style CUDA source code will either fail to compile or will not behave as originally intended.
  • Interoperability with rendering languages such as OpenGL is one-way, with OpenGL having access to registered CUDA memory but CUDA not having access to OpenGL memory.
  • Copying between host and device memory may incur a performance hit due to system bus bandwidth and latency (this can be partly alleviated with asynchronous memory transfers, handled by the GPU's DMA engine).
  • Threads should be running in groups of at least 32 for best performance, with total number of threads numbering in the thousands. Branches in the program code do not affect performance significantly, provided that each of 32 threads takes the same execution path; theSIMD execution model becomes a significant limitation for any inherently divergent task (e.g. traversing aspace partitioning data structure duringray tracing).
  • No emulation or fallback functionality is available for modern revisions.
  • Valid C++ may sometimes be flagged and prevent compilation due to the way the compiler approaches optimization for target GPU device limitations.[citation needed]
  • C++run-time type information (RTTI) and C++-style exception handling are only supported in host code, not in device code.
  • Insingle-precision on first generation CUDA compute capability 1.x devices,denormal numbers are unsupported and are instead flushed to zero, and the precision of both the division and square root operations are slightly lower than IEEE 754-compliant single precision math. Devices that support compute capability 2.0 and above support denormal numbers, and the division and square root operations are IEEE 754 compliant by default. However, users can obtain the prior faster gaming-grade math of compute capability 1.x devices if desired by setting compiler flags to disable accurate divisions and accurate square roots, and enable flushing denormal numbers to zero.[31]
  • UnlikeOpenCL, CUDA-enabled GPUs are only available from Nvidia as it is proprietary.[32][3] Attempts to implement CUDA on other GPUs include:
    • Project Coriander: Converts CUDA C++11 source to OpenCL 1.2 C. A fork of CUDA-on-CL intended to runTensorFlow.[33][34][35]
    • CU2CL: Convert CUDA 3.2 C++ to OpenCL C.[36]
    • GPUOpen HIP: A thin abstraction layer on top of CUDA andROCm intended for AMD and Nvidia GPUs. Has a conversion tool for importing CUDA C++ source. Supports CUDA 4.0 plus C++11 and float16.
    • ZLUDA is a drop-in replacement for CUDA on AMD GPUs and formerly Intel GPUs with near-native performance.[37] The developer, Andrzej Janik, was separately contracted by both Intel and AMD to develop the software in 2021 and 2022, respectively. However, neither company decided to release it officially due to the lack of a business use case. AMD's contract included a clause that allowed Janik to release his code for AMD independently, allowing him to release the new version that only supports AMD GPUs.[38]
    • chipStar can compile and run CUDA/HIP programs on advanced OpenCL 3.0 or Level Zero platforms.[39]
    • SCALE is a CUDA-compatible programming toolkit for ahead of time compilation of CUDA source code on AMD GPUs, aiming to expand support for other GPUs in the future.[40]

Example

[edit]

This example code inC++ loads a texture from an image into an array on the GPU:

texture<float,2,cudaReadModeElementType>tex;voidfoo(){cudaArray*cu_array;// Allocate arraycudaChannelFormatDescdescription=cudaCreateChannelDesc<float>();cudaMallocArray(&cu_array,&description,width,height);// Copy image data to arraycudaMemcpyToArray(cu_array,image,width*height*sizeof(float),cudaMemcpyHostToDevice);// Set texture parameters (default)tex.addressMode[0]=cudaAddressModeClamp;tex.addressMode[1]=cudaAddressModeClamp;tex.filterMode=cudaFilterModePoint;tex.normalized=false;// do not normalize coordinates// Bind the array to the texturecudaBindTextureToArray(tex,cu_array);// Run kerneldim3blockDim(16,16,1);dim3gridDim((width+blockDim.x-1)/blockDim.x,(height+blockDim.y-1)/blockDim.y,1);kernel<<<gridDim,blockDim,0>>>(d_data,height,width);// Unbind the array from the texturecudaUnbindTexture(tex);}__global__voidkernel(float*odata,intheight,intwidth){unsignedintx=blockIdx.x*blockDim.x+threadIdx.x;unsignedinty=blockIdx.y*blockDim.y+threadIdx.y;if(x<width&&y<height){floatc=tex2D(tex,x,y);odata[y*width+x]=c;}}

Below is an example given inPython that computes the product of two arrays on the GPU. The unofficial Python language bindings can be obtained fromPyCUDA.[41]

importnumpyimportpycuda.autoinitfromnumpy.typingimportNDArray,float32frompycuda.compilerimportSourceModulefrompycuda.driverimportFunction,In,Outmod:SourceModule=SourceModule("""__global__ void multiply_them(float* dest, float* a, float* b) {    const int i = threadIdx.x;    dest[i] = a[i] * b[i];}""")multiply_them:Function=mod.get_function("multiply_them")a:NDArray[float32]=numpy.random.randn(400).astype(numpy.float32)b:NDArray[float32]=numpy.random.randn(400).astype(numpy.float32)dest:NDArray[float32]=numpy.zeros_like(a)multiply_them(Out(dest),In(a),In(b),block=(400,1,1))print(dest-a*b)

Additional Python bindings to simplify matrix multiplication operations can be found in the programpycublas.[42]

importnumpyfrompycublasimportCUBLASMatrixA:CUBLASMatrix=CUBLASMatrix(numpy.mat([[1,2,3],[4,5,6]],numpy.float32))B:CUBLASMatrix=CUBLASMatrix(numpy.mat([[2,3],[4,5],[6,7]],numpy.float32))C:CUBLASMatrix=A*Bprint(C.np_mat())

whileCuPy directly replaces NumPy:[43]

importcupyfromcupy.typingimportNDArray,float64a:NDArray[float64]=cupy.random.randn(400)b:NDArray[float64]=cupy.random.randn(400)dest:NDArray[float64]=cupy.zeros_like(a)print(dest-a*b)

GPUs supported

[edit]

Note on notation: compute capacity X.Y is also written SMXY or sm_XY (e.g. 10.3 as SM103 or sm_103) in professional Nvidia software and the code Nvidia has contributed to LLVM.[44]

Below is a table of supported CUDA compute capabilities based on the CUDA SDK version and microarchitecture, listed by code name:

CUDA SDK support vs. microarchitecture (cell: compute capacity)
CUDA SDK
version(s)		TeslaFermiKepler
(early)		Kepler
(late)		MaxwellPascalVoltaTuringAmpereAda
Lovelace		HopperBlackwell
1.0[45]1.0 – 1.1
1.11.0 – 1.1+x
2.01.0 – 1.1+x
2.1 – 2.3.1[46][47][48][49]1.0 – 1.3
3.0 – 3.1[50][51]1.02.0
3.2[52]1.02.1
4.0 – 4.21.02.1
5.0 – 5.51.03.03.5
6.01.03.23.5
6.51.13.75.x
7.0 – 7.52.05.x
8.02.06.x
9.0 – 9.23.07.0 – 7.2
10.0 – 10.23.07.5
11.0[53]3.58.0
11.1 – 11.4[54]3.58.6
11.5 – 11.7.1[55]3.58.7
11.8[56]3.58.99.0
12.0 – 12.65.09.0
12.85.012.0
12.95.012.1
13.0[57]7.512.1

Note: CUDA SDK 10.2 is the last official release for macOS, as support will not be available for macOS in newer releases.

CUDA compute capability by version with associated GPU semiconductors and GPU card models (separated by their various application areas):

GPU semiconductors and Nvidia GPU board products sorted by compute capability
Compute
capability
(version)		Micro-
architecture		GPUsGeForceQuadro,NVSTesla/DatacenterTegra,
Jetson,
DRIVE
1.0TeslaG80GeForce 8800 Ultra, GeForce 8800 GTX, GeForce 8800 GTS(G80)Quadro FX 5600, Quadro FX 4600, Quadro Plex 2100 S4Tesla C870, Tesla D870, Tesla S870
1.1G92, G94, G96, G98, G84, G86GeForce GTS 250, GeForce 9800 GX2, GeForce 9800 GTX, GeForce 9800 GT, GeForce 8800 GTS(G92), GeForce 8800 GT, GeForce 9600 GT, GeForce 9500 GT, GeForce 9400 GT, GeForce 8600 GTS, GeForce 8600 GT, GeForce 8500 GT,
GeForce G110M, GeForce 9300M GS, GeForce 9200M GS, GeForce 9100M G, GeForce 8400M GT, GeForce G105M		Quadro FX 4700 X2, Quadro FX 3700, Quadro FX 1800, Quadro FX 1700, Quadro FX 580, Quadro FX 570, Quadro FX 470, Quadro FX 380, Quadro FX 370, Quadro FX 370 Low Profile, Quadro NVS 450, Quadro NVS 420, Quadro NVS 290, Quadro NVS 295, Quadro Plex 2100 D4,
Quadro FX 3800M, Quadro FX 3700M, Quadro FX 3600M, Quadro FX 2800M, Quadro FX 2700M, Quadro FX 1700M, Quadro FX 1600M, Quadro FX 770M, Quadro FX 570M, Quadro FX 370M, Quadro FX 360M, Quadro NVS 320M, Quadro NVS 160M, Quadro NVS 150M, Quadro NVS 140M, Quadro NVS 135M, Quadro NVS 130M, Quadro NVS 450, Quadro NVS 420,[58] Quadro NVS 295
1.2GT218, GT216, GT215GeForce GT 340*, GeForce GT 330*, GeForce GT 320*, GeForce 315*, GeForce 310*, GeForce GT 240, GeForce GT 220, GeForce 210,
GeForce GTS 360M, GeForce GTS 350M, GeForce GT 335M, GeForce GT 330M, GeForce GT 325M, GeForce GT 240M, GeForce G210M, GeForce 310M, GeForce 305M		Quadro FX 380 Low Profile, Quadro FX 1800M, Quadro FX 880M, Quadro FX 380M,
Nvidia NVS 300, NVS 5100M, NVS 3100M, NVS 2100M, ION
1.3GT200, GT200bGeForce GTX 295, GTX 285, GTX 280, GeForce GTX 275, GeForce GTX 260Quadro FX 5800, Quadro FX 4800, Quadro FX 4800 for Mac, Quadro FX 3800, Quadro CX, Quadro Plex 2200 D2Tesla C1060, Tesla S1070, Tesla M1060
2.0FermiGF100, GF110GeForce GTX 590, GeForce GTX 580, GeForce GTX 570, GeForce GTX 480, GeForce GTX 470, GeForce GTX 465,
GeForce GTX 480M		Quadro 6000, Quadro 5000, Quadro 4000, Quadro 4000 for Mac, Quadro Plex 7000,
Quadro 5010M, Quadro 5000M		Tesla C2075, Tesla C2050/C2070, Tesla M2050/M2070/M2075/M2090
2.1GF104, GF106 GF108, GF114, GF116, GF117, GF119GeForce GTX 560 Ti, GeForce GTX 550 Ti, GeForce GTX 460, GeForce GTS 450, GeForce GTS 450*, GeForce GT 640 (GDDR3), GeForce GT 630, GeForce GT 620, GeForce GT 610, GeForce GT 520, GeForce GT 440, GeForce GT 440*, GeForce GT 430, GeForce GT 430*, GeForce GT 420*,
GeForce GTX 675M, GeForce GTX 670M, GeForce GT 635M, GeForce GT 630M, GeForce GT 625M, GeForce GT 720M, GeForce GT 620M, GeForce 710M, GeForce 610M, GeForce 820M, GeForce GTX 580M, GeForce GTX 570M, GeForce GTX 560M, GeForce GT 555M, GeForce GT 550M, GeForce GT 540M, GeForce GT 525M, GeForce GT 520MX, GeForce GT 520M, GeForce GTX 485M, GeForce GTX 470M, GeForce GTX 460M, GeForce GT 445M, GeForce GT 435M, GeForce GT 420M, GeForce GT 415M, GeForce 710M, GeForce 410M		Quadro 2000, Quadro 2000D, Quadro 600,
Quadro 4000M, Quadro 3000M, Quadro 2000M, Quadro 1000M,
NVS 310, NVS 315, NVS 5400M, NVS 5200M, NVS 4200M
3.0KeplerGK104, GK106, GK107GeForce GTX 770, GeForce GTX 760, GeForce GT 740, GeForce GTX 690, GeForce GTX 680, GeForce GTX 670, GeForce GTX 660 Ti, GeForce GTX 660, GeForce GTX 650 Ti BOOST, GeForce GTX 650 Ti, GeForce GTX 650,
GeForce GTX 880M, GeForce GTX 870M, GeForce GTX 780M, GeForce GTX 770M, GeForce GTX 765M, GeForce GTX 760M, GeForce GTX 680MX, GeForce GTX 680M, GeForce GTX 675MX, GeForce GTX 670MX, GeForce GTX 660M, GeForce GT 750M, GeForce GT 650M, GeForce GT 745M, GeForce GT 645M, GeForce GT 740M, GeForce GT 730M, GeForce GT 640M, GeForce GT 640M LE, GeForce GT 735M, GeForce GT 730M		Quadro K5000, Quadro K4200, Quadro K4000, Quadro K2000, Quadro K2000D, Quadro K600, Quadro K420,
Quadro K500M, Quadro K510M, Quadro K610M, Quadro K1000M, Quadro K2000M, Quadro K1100M, Quadro K2100M, Quadro K3000M, Quadro K3100M, Quadro K4000M, Quadro K5000M, Quadro K4100M, Quadro K5100M,
NVS 510, Quadro 410		Tesla K10, GRID K340, GRID K520, GRID K2
3.2GK20ATegra K1,
Jetson TK1
3.5GK110, GK208GeForce GTX Titan Z, GeForce GTX Titan Black, GeForce GTX Titan, GeForce GTX 780 Ti, GeForce GTX 780, GeForce GT 640 (GDDR5), GeForce GT 630 v2, GeForce GT 730, GeForce GT 720, GeForce GT 710, GeForce GT 740M (64-bit, DDR3), GeForce GT 920MQuadro K6000, Quadro K5200Tesla K40, Tesla K20x, Tesla K20
3.7GK210Tesla K80
5.0MaxwellGM107, GM108GeForce GTX 750 Ti, GeForce GTX 750, GeForce GTX 960M, GeForce GTX 950M, GeForce 940M, GeForce 930M, GeForce GTX 860M, GeForce GTX 850M, GeForce 845M, GeForce 840M, GeForce 830MQuadro K1200, Quadro K2200, Quadro K620, Quadro M2000M, Quadro M1000M, Quadro M600M, Quadro K620M, NVS 810Tesla M10
5.2GM200, GM204, GM206GeForce GTX Titan X, GeForce GTX 980 Ti, GeForce GTX 980, GeForce GTX 970, GeForce GTX 960, GeForce GTX 950, GeForce GTX 750 SE,
GeForce GTX 980M, GeForce GTX 970M, GeForce GTX 965M		Quadro M6000 24GB, Quadro M6000, Quadro M5000, Quadro M4000, Quadro M2000, Quadro M5500,
Quadro M5000M, Quadro M4000M, Quadro M3000M		Tesla M4, Tesla M40, Tesla M6, Tesla M60
5.3GM20BTegra X1,
Jetson TX1,
Jetson Nano,
DRIVE CX,
DRIVE PX
6.0PascalGP100Quadro GP100Tesla P100
6.1GP102, GP104, GP106, GP107, GP108Nvidia TITAN Xp, Titan X,
GeForce GTX 1080 Ti, GTX 1080, GTX 1070 Ti, GTX 1070, GTX 1060,
GTX 1050 Ti, GTX 1050, GT 1030, GT 1010,
MX350, MX330, MX250, MX230, MX150, MX130, MX110		Quadro P6000, Quadro P5000, Quadro P4000, Quadro P2200, Quadro P2000, Quadro P1000, Quadro P400, Quadro P500, Quadro P520, Quadro P600,
Quadro P5000 (mobile), Quadro P4000 (mobile), Quadro P3000 (mobile)		Tesla P40, Tesla P6, Tesla P4
6.2GP10B[59]Tegra X2, Jetson TX2, DRIVE PX 2
7.0VoltaGV100NVIDIA TITAN VQuadro GV100Tesla V100, Tesla V100S
7.2GV10B[60]

GV11B[61][62]

Tegra Xavier,
Jetson Xavier NX,
Jetson AGX Xavier,
DRIVE AGX Xavier,
DRIVE AGX Pegasus,
Clara AGX
7.5TuringTU102, TU104, TU106, TU116, TU117NVIDIA TITAN RTX,
GeForce RTX 2080 Ti, RTX 2080 Super, RTX 2080, RTX 2070 Super, RTX 2070, RTX 2060 Super, RTX 2060 12GB, RTX 2060,
GeForce GTX 1660 Ti, GTX 1660 Super, GTX 1660, GTX 1650 Super, GTX 1650, MX550, MX450		Quadro RTX 8000, Quadro RTX 6000, Quadro RTX 5000, Quadro RTX 4000, T1000, T600, T400
T1200 (mobile), T600 (mobile), T500 (mobile), Quadro T2000 (mobile), Quadro T1000 (mobile)		Tesla T4
8.0AmpereGA100A100 80GB, A100 40GB, A30
8.6GA102, GA103, GA104, GA106, GA107GeForce RTX 3090 Ti, RTX 3090, RTX 3080 Ti, RTX 3080 12GB, RTX 3080, RTX 3070 Ti, RTX 3070, RTX 3060 Ti, RTX 3060, RTX 3050, RTX 3050 Ti (mobile), RTX 3050 (mobile), RTX 2050 (mobile), MX570RTX A6000, RTX A5500, RTX A5000, RTX A4500, RTX A4000, RTX A2000
RTX A5000 (mobile), RTX A4000 (mobile), RTX A3000 (mobile), RTX A2000 (mobile)		A40, A16, A10, A2
8.7GA10BJetson Orin Nano,
Jetson Orin NX,
Jetson AGX Orin,
DRIVE AGX Orin,
IGX Orin
8.9Ada Lovelace[63]AD102, AD103, AD104, AD106, AD107GeForce RTX 4090, RTX 4080 Super, RTX 4080, RTX 4070 Ti Super, RTX 4070 Ti, RTX 4070 Super, RTX 4070, RTX 4060 Ti, RTX 4060, RTX 4050 (mobile)RTX 6000 Ada, RTX 5880 Ada, RTX 5000 Ada, RTX 4500 Ada, RTX 4000 Ada, RTX 4000 SFF Ada, RTX 2000 Ada, RTX 5000 Ada (mobile), RTX 4000 Ada (mobile), RTX 3500 Ada (mobile), RTX 2000 Ada (mobile)L40S, L40, L20, L4, L2
9.0HopperGH100H200, H100, GH200
10.0BlackwellGB100B200, B100, GB200
10.3GB200B300, GB300
11.0[a]Jetson AGX Thor,
DRIVE AGX Thor
12.0GB202, GB203, GB205, GB206, GB207GeForce RTX 5090, RTX 5080, RTX 5070 Ti, RTX 5070, RTX 5060 Ti, RTX 5060, RTX 5050RTX PRO 6000 Blackwell Workstation, RTX PRO 5000 Blackwell, RTX PRO 4500 Blackwell, RTX PRO 4000 BlackwellRTX PRO 6000 Blackwell Server
12.1GB10DGX Spark
Compute
capability
(version)		Micro-
architecture		GPUsGeForceQuadro,NVSTesla/DatacenterTegra,
Jetson,
DRIVE

* –OEM-only products

  1. ^CUDA Toolkit 13.0 renamed the SM101 for Thor GPUs to SM110.

Version features and specifications

[edit]

Note: GPU with a higher compute capacity is able to execute PTX code meant for GPU of a lower range of compute capacities. However, it is possible to compile CUDA code into a form that only works on one family (same "X") of GPUs; if existing code is compiled this way, recompilation will be needed for it to work on a newer GPU.[44]

Feature support (unlisted features are supported for all compute capabilities)Compute capability (version)
1.0, 1.11.2, 1.32.x3.03.23.5, 3.7, 5.x, 6.x, 7.0, 7.27.58.x9.0, 10.x, 12.x
Warp vote functions (__all(), __any())NoYes
Warp vote functions (__ballot())NoYes
Memory fence functions (__threadfence_system())
Synchronization functions (__syncthreads_count(), __syncthreads_and(), __syncthreads_or())
Surface functions
3D grid of thread blocks
Warp shuffle functionsNoYes
Unified memory programming
Funnel shiftNoYes
Dynamic parallelismNoYes
Uniform Datapath[64]NoYes
Hardware-accelerated async-copyNoYes
Hardware-acceleratedsplit arrive/wait barrier
Warp-level support for reduction ops
L2 cache residency management
DPX instructions for accelerated dynamic programmingNoYes
Distributed shared memory
Thread block cluster
Tensor memory accelerator (TMA) unit
Feature support (unlisted features are supported for all compute capabilities)1.0, 1.11.2, 1.32.x3.03.23.5, 3.7, 5.x, 6.x, 7.0, 7.27.58.x9.0, 10.x, 12.x
Compute capability (version)

[65]

Data types

[edit]

Floating-point types

[edit]
Data typeSupported vector typesStorage Length Bits
(complete vector)		Used Length Bits
(single value)		Sign BitsExponent BitsMantissa BitsComments
E2M1 = FP4e2m1x2 / e2m1x48 / 164121
E2M3 = FP6 variante2m3x2 / e2m3x416 / 326123
E3M2 = FP6 variante3m2x2 / e3m2x416 / 326132
UE4M3ue4m387043Used for scaling (E2M1 only)
E4M3 = FP8 variante4m3 / e4m3x2 / e4m3x48 / 16 / 328143
E5M2 = FP8 variante5m2 / e5m2x2 / e5m2x48 / 16 / 328152Exponent/range of FP16, fits into 8 bits
UE8M0ue8m0x2168080Used for scaling (any FP4 or FP6 or FP8 format)
FP16f16 / f16x216 / 32161510
BF16bf16 / bf16x216 / 3216187Exponent/range of FP32, fits into 16 bits
TF32tf3232191810Exponent/range of FP32, mantissa/precision of FP16
FP32f32 / f32x232 / 64321823
FP64f64646411152

Version support

[edit]
Data typeBasic OperationsSupported since
Atomic OperationsSupported since
for global memory		Supported since
for shared memory
8-bit integer
signed/unsigned		loading, storing, conversion1.0——
16-bit integer
signed/unsigned		general operations1.0atomicCAS()3.5
32-bit integer
signed/unsigned		general operations1.0atomic functions1.11.2
64-bit integer
signed/unsigned		general operations1.0atomic functions1.22.0
any 128-bit trivially copyable typegeneral operationsNoatomicExch, atomicCAS9.0
16-bit floating point
FP16		addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion		5.3half2 atomic addition6.0
atomic addition7.0
16-bit floating point
BF16		addition, subtraction,
multiplication, comparison,
warp shuffle functions, conversion		8.0atomic addition8.0
32-bit floating pointgeneral operations1.0atomicExch()1.11.2
atomic addition2.0
32-bit floating point float2 and float4general operationsNoatomic addition9.0
64-bit floating pointgeneral operations1.3atomic addition6.0

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[66]

Tensor cores

[edit]
FMA per cycle per tensor core[67]Supported since7.07.27.5 Workstation7.5 Desktop8.08.6 Workstation8.78.6 Desktop8.9 Desktop8.9 Workstation9.010.010.112.0
Data TypeFor dense matricesFor sparse matrices1st Gen (8x/SM)1st Gen? (8x/SM)2nd Gen (8x/SM)3rd Gen (4x/SM)4th Gen (4x/SM)5th Gen (4x/SM)
1-bit values (AND)8.0 as
experimental		NoNo40962048speed tbd
1-bit values (XOR)7.5–8.9 as
experimental		No1024Deprecated or removed?
4-bit integers8.0–8.9 as
experimental		2561024512
4-bit floating point FP4 (E2M1)10.0No4096tbd512
6-bit floating point FP6 (E3M2 and E2M3)10.0No2048tbd
8-bit integers7.28.0No12812851225610242048256
8-bit floating point FP8 (E4M3 and E5M2) with FP16 accumulate8.9No256
8-bit floating point FP8 (E4M3 and E5M2) with FP32 accumulate128128
16-bit floating point FP16 with FP16 accumulate7.08.06464642561285121024128
16-bit floating point FP16 with FP32 accumulate326412864
16-bit floating point BF16 with FP32 accumulate7.5[68]8.0No64[69]
32-bit (19 bits used) floating point TF32speed tbd (32?)[69]128326425651232
64-bit floating point8.0NoNo16speed tbd3216tbd

Note: Any missing lines or empty entries do reflect some lack of information on that exact item.[70][71][72][73][74][75]

Tensor Core Composition7.07.2, 7.58.0, 8.68.78.99.0
Dot Product Unit Width in FP16 units (in bytes)[76][77][78][79]4 (8)8 (16)4 (8)16 (32)
Dot Product Units per Tensor Core1632
Tensor Cores per SM partition21
Full throughput (Bytes/cycle)[80] per SM partition[81]2565122561024
FP Tensor Cores: Minimum cycles for warp-wide matrix calculation848
FP Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)[82]2048
INT Tensor Cores: Minimum cycles for warp-wide matrix calculationNo4
INT Tensor Cores: Minimum Matrix Shape for full throughput (Bytes)No102420481024

[83][84][85][86]

FP64 Tensor Core Composition8.08.68.78.99.0
Dot Product Unit Width in FP64 units (in bytes)4 (32)tbd4 (32)
Dot Product Units per Tensor Core4tbd8
Tensor Cores per SM partition1
Full throughput (Bytes/cycle)[80] per SM partition[81]128tbd256
Minimum cycles for warp-wide matrix calculation16tbd
Minimum Matrix Shape for full throughput (Bytes)[82]2048

Technical specifications

[edit]
Technical specificationsCompute capability (version)
1.01.11.21.32.x3.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.010.x12.x
Maximum number of resident grids per device
(concurrent kernel execution, can be lower for specific devices)		11643216128321612816128
Maximum dimensionality of grid of thread blocks23
Maximum x-dimension of a grid of thread blocks65535231 − 1
Maximum y-, or z-dimension of a grid of thread blocks65535
Maximum dimensionality of thread block3
Maximum x- or y-dimension of a block5121024
Maximum z-dimension of a block64
Maximum number of threads per block5121024
Warp size32
Maximum number of resident blocks per multiprocessor816321632162432
Maximum number of resident warps per multiprocessor243248643264486448
Maximum number of resident threads per multiprocessor76810241536204810242048153620481536
Number of 32-bit regular registers per multiprocessor8 K16 K32 K64 K128 K64 K
Number of 32-bit uniform registers per multiprocessorNo2 K[87]

[88]

Maximum number of 32-bit registers per thread block8 K16 K32 K64 K32 K64 K32 K64 K32 K64 K
Maximum number of 32-bit regular registers per thread12463255
Maximum number of 32-bit uniform registers per warpNo63[87]

[89]

Amount of shared memory per multiprocessor
(out of overall shared memory + L1 cache, where applicable)		16 KiB16 / 48 KiB (of 64 KiB)16 / 32 / 48 KiB (of 64 KiB)80 / 96 / 112 KiB (of 128 KiB)64 KiB96 KiB64 KiB96 KiB64 KiB0 / 8 / 16 / 32 / 64 / 96 KiB (of 128 KiB)32 / 64 KiB (of 96 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 KiB (of 192 KiB)0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)0 / 8 / 16 / 32 / 64 / 100 / 132 / 164 / 196 / 228 KiB (of 256 KiB)0 / 8 / 16 / 32 / 64 / 100 KiB (of 128 KiB)
Maximum amount of shared memory per thread block16 KiB48 KiB96 KiB48 KiB64 KiB163 KiB99 KiB163 KiB99 KiB227 KiB99 KiB
Number of shared memory banks1632
Amount of local memory per thread16 KiB512 KiB
Constant memory size accessible by CUDA C/C++
(1 bank, PTX can access 11 banks, SASS can access 18 banks)		64 KiB
Cache working set per multiprocessor for constant memory8 KiB4 KiB8 KiB
Cache working set per multiprocessor for texture memory16 KiB per TPC24 KiB per TPC12 KiB12 – 48 KiB[90]24 KiB48 KiB32 KiB[91]24 KiB48 KiB24 KiB32 – 128 KiB32 – 64 KiB28 – 192 KiB28 – 128 KiB28 – 192 KiB28 – 128 KiB28 – 256 KiB
Maximum width for 1D texture reference bound to a CUDA
array		819265536131072
Maximum width for 1D texture reference bound to linear
memory		227228227228227228
Maximum width and number of layers for a 1D layered
texture reference		8192 × 51216384 × 204832768 x 2048
Maximum width and height for 2D texture reference bound
to a CUDA array		65536 × 3276865536 × 65535131072 x 65536
Maximum width and height for 2D texture reference bound
to a linear memory		65000 x 6500065536 x 65536131072 x 65000
Maximum width and height for 2D texture reference bound
to a CUDA array supporting texture gather		—16384 x 1638432768 x 32768
Maximum width, height, and number of layers for a 2D
layered texture reference		8192 × 8192 × 51216384 × 16384 × 204832768 x 32768 x 2048
Maximum width, height and depth for a 3D texture
reference bound to linear memory or a CUDA array		2048340963163843
Maximum width (and height) for a cubemap texture reference—1638432768
Maximum width (and height) and number of layers
for a cubemap layered texture reference		—16384 × 204632768 × 2046
Maximum number of textures that can be bound to a
kernel		128256
Maximum width for a 1D surface reference bound to a
CUDA array		Not
supported		655361638432768
Maximum width and number of layers for a 1D layered
surface reference		65536 × 204816384 × 204832768 × 2048
Maximum width and height for a 2D surface reference
bound to a CUDA array		65536 × 3276816384 × 65536131072 × 65536
Maximum width, height, and number of layers for a 2D
layered surface reference		65536 × 32768 × 204816384 × 16384 × 204832768 × 32768 × 2048
Maximum width, height, and depth for a 3D surface
reference bound to a CUDA array		65536 × 32768 × 20484096 × 4096 × 409616384 × 16384 × 16384
Maximum width (and height) for a cubemap surface reference bound to a CUDA array327681638432768
Maximum width and number of layers for a cubemap
layered surface reference		32768 × 204616384 × 204632768 × 2046
Maximum number of surfaces that can be bound to a
kernel		81632
Maximum number of instructions per kernel2 million512 million
Maximum number of Thread Blocks per Thread Block Cluster[92]No168
Technical specifications1.01.11.21.32.x3.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.010.x12.x
Compute capability (version)
[93][94]

Multiprocessor architecture

[edit]
Architecture specificationsCompute capability (version)
1.01.11.21.32.02.13.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.010.x12.x
Number of ALU lanes for INT32 arithmetic operations83248192[95]12812864128128646464128
Number of ALU lanes for any INT32 or FP32 arithmetic operation——
Number of ALU lanes for FP32 arithmetic operations6464128128
Number of ALU lanes for FP16x2 arithmetic operationsNo1128[96]128[97]64[98]
Number of ALU lanes for FP64 arithmetic operationsNo116 by FP32[99]4 by FP32[100]88 / 64[101]644[102]324322322642
Number of Load/Store Units4 per 2 SM8 per 2 SM8 per 2 SM / 3 SM[101]8 per 3 SM163216321632
Number of special function units for single-precision floating-point transcendental functions2[103]4832163216
Number of texture mapping units (TMU)4 per 2 SM8 per 2 SM8 per 2 / 3SM[101]8 per 3 SM44 / 8[101]1681684
Number of ALU lanes for uniform INT32 arithmetic operationsNo2[104]
Number of tensor coresNo8 (1st gen.)[105]0 / 8[101] (2nd gen.)4 (3rd gen.)4 (4th gen.)
Number of raytracing coresNo0 / 1[101] (1st gen.)No1 (2nd gen.)No1 (3rd gen.)No
Number of SM Partitions = Processing Blocks[106]1424
Number of warp schedulers per SM partition1241
Max number of new instructions issued each cycle by a single scheduler[107]2[108]12[109]21
Size of unified memory for data cache and shared memory16 KiB[110]16 KiB[110]64 KiB128 KiB64 KiB SM + 24 KiB L1 (separate)[111]96 KiB SM + 24 KiB L1 (separate)[111]64 KiB SM + 24 KiB L1 (separate)[111]64 KiB SM + 24 KiB L1 (separate)[111]96 KiB SM + 24 KiB L1 (separate)[111]64 KiB SM + 24 KiB L1 (separate)[111]128 KiB96 KiB[112]192 KiB128 KiB192 KiB128 KiB256 KiB
Size of L3 instruction cache per GPU32 KiB[113]use L2 Data Cache
Size of L2 instruction cache per Texture Processor Cluster (TPC)8 KiB
Size of L1.5 instruction cache per SM[114]4 KiB32 KiB32 KiB48 KiB[91]128 KiB32 KiB128 KiB~46 KiB[115]128 KiB[116]
Size of L1 instruction cache per SM8 KiB8 KiB
Size of L0 instruction cache per SM partitiononly 1 partition per SMNo12 KiB16 KiB?[117]32 KiB
Instruction Width[114]32 bits instructions and 64 bits instructions[118]64 bits instructions + 64 bits control logic every 7 instructions64 bits instructions + 64 bits control logic every 3 instructions128 bits combined instruction and control logic
Memory Bus Width per Memory Partition in bits64 ((G)DDR)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)32 ((G)DDR)512 (HBM)32 ((G)DDR)
L2 Cache per Memory Partition16 KiB[119]32 KiB[119]128 KiB256 KiB1 MiB512 KiB128 KiB512 KiB256 KiB128 KiB768 KiB64 KiB512 KiB4 MiB512 KiB8 MiB[120]5 MiB6.25 MiB8 MiB[121]
Number of Render Output Units (ROP) per memory partition (or per GPC in later models)4848168128416281616 per GPC3 per GPC16 per GPC
Architecture specifications1.01.11.21.32.02.13.03.23.53.75.05.25.36.06.16.27.07.27.58.08.68.78.99.010.x12.x
Compute capability (version)

For more information read the Nvidia CUDA C++ Programming Guide.[122]

Usages of CUDA architecture

[edit]

Comparison with competitors

[edit]

CUDA competes with other GPU computing stacks:Intel OneAPI andAMD ROCm.

Whereas Nvidia's CUDA is closed-source, Intel's OneAPI and AMD's ROCm are open source.

Intel OneAPI

[edit]
Main article:OneAPI (compute acceleration)

oneAPI is an initiative based in open standards, created to support software development for multiple hardware architectures.[125] The oneAPI libraries must implement open specifications that are discussed publicly by the Special Interest Groups, offering the possibility for any developer or organization to implement their own versions of oneAPI libraries.[126][127]

Originally made by Intel, other hardware adopters include Fujitsu and Huawei.

Unified Acceleration Foundation (UXL)

[edit]

Unified Acceleration Foundation (UXL) is a new technology consortium working on the continuation of the OneAPI initiative, with the goal to create a new open standard accelerator software ecosystem, related open standards and specification projects through Working Groups and Special Interest Groups (SIGs). The goal is to offer open alternatives to Nvidia's CUDA. The main companies behind it are Intel, Google, ARM, Qualcomm, Samsung, Imagination, and VMware.[128]

AMD ROCm

[edit]
Main article:ROCm

ROCm[129] is an open source software stack forgraphics processing unit (GPU) programming fromAdvanced Micro Devices (AMD).

See also

[edit]

References

[edit]
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  7. ^abAbi-Chahla, Fedy (June 18, 2008)."Nvidia's CUDA: The End of the CPU?". Tom's Hardware. RetrievedMay 17, 2015.
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  11. ^abCosgrove, Emma."Ian Buck built Nvidia's secret weapon. He may spend the rest of his career defending it".Business Insider. Retrieved2025-07-24.
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  91. ^ab"Tegra X1". 9 January 2015.
  92. ^NVIDIA H100 Tensor Core GPU Architecture
  93. ^H.1. Features and Technical Specifications – Table 14. Technical Specifications per Compute Capability
  94. ^NVIDIA Hopper Architecture In-Depth
  95. ^can only execute 160 integer instructions according to programming guide
  96. ^128 according to[1]. 64 from FP32 + 64 separate units?
  97. ^64 by FP32 cores and 64 by flexible FP32/INT cores.
  98. ^"CUDA C++ Programming Guide".docs.nvidia.com.
  99. ^32 FP32 lanes combine to 16 FP64 lanes. Maybe lower depending on model.
  100. ^only supported by 16 FP32 lanes, they combine to 4 FP64 lanes
  101. ^abcdefdepending on model
  102. ^Effective speed, probably over FP32 ports. No description of actual FP64 cores.
  103. ^Can also be used for integer additions and comparisons
  104. ^2 clock cycles/instruction for each SM partitionBurgess, John (2019). "RTX ON – The NVIDIA TURING GPU".2019 IEEE Hot Chips 31 Symposium (HCS). pp. 1–27.doi:10.1109/HOTCHIPS.2019.8875651.ISBN 978-1-7281-2089-8.S2CID 204822166.
  105. ^Durant, Luke; Giroux, Olivier; Harris, Mark; Stam, Nick (May 10, 2017)."Inside Volta: The World's Most Advanced Data Center GPU".Nvidia developer blog.
  106. ^The schedulers and dispatchers have dedicated execution units unlike with Fermi and Kepler.
  107. ^Dispatching can overlap concurrently, if it takes more than one cycle (when there are less execution units than 32/SM Partition)
  108. ^Can dual issue MAD pipe and SFU pipe
  109. ^No more than one scheduler can issue 2 instructions at once. The first scheduler is in charge of warps with odd IDs. The second scheduler is in charge of warps with even IDs.
  110. ^abshared memory only, no data cache
  111. ^abcdefshared memory separate, but L1 includes texture cache
  112. ^"H.6.1. Architecture".docs.nvidia.com. Retrieved2019-05-13.
  113. ^Wong, Henry; Papadopoulou, Misel-Myrto; Sadooghi-Alvandi, Maryam; Moshovos, Andreas (March 2010).Demystifying GPU Microarchitecture through Microbenchmarking(PDF). 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS). White Plains, NY, USA: IEEE Computer Society.doi:10.1109/ISPASS.2010.5452013.ISBN 978-1-4244-6023-6.
  114. ^abJia, Zhe; Maggioni, Marco; Staiger, Benjamin; Scarpazza, Daniele P. (2018). "Dissecting the NVIDIA Volta GPU Architecture via Microbenchmarking".arXiv:1804.06826 [cs.DC].
  115. ^Jia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking".arXiv:1903.07486 [cs.DC].
  116. ^"Dissecting the Ampere GPU Architecture through Microbenchmarking".
  117. ^Note thatJia, Zhe; Maggioni, Marco; Smith, Jeffrey; Daniele Paolo Scarpazza (2019). "Dissecting the NVidia Turing T4 GPU via Microbenchmarking".arXiv:1903.07486 [cs.DC]. disagrees and states 2 KiB L0 instruction cache per SM partition and 16 KiB L1 instruction cache per SM
  118. ^"asfermi Opcode".GitHub.
  119. ^abfor access with texture engine only
  120. ^25% disabled on RTX 4060, RTX 4070, RTX 4070 Ti and RTX 4090
  121. ^25% disabled on RTX 5070 Ti and RTX 5090
  122. ^"CUDA C++ Programming Guide, Compute Capabilities".docs.nvidia.com. Retrieved2025-02-06.
  123. ^"nVidia CUDA Bioinformatics: BarraCUDA".BioCentric. 2019-07-19. Retrieved2019-10-15.
  124. ^"Part V: Physics Simulation".NVIDIA Developer. Retrieved2020-09-11.
  125. ^"oneAPI Programming Model".oneAPI.io. Retrieved2024-07-27.
  126. ^"Specifications | oneAPI".oneAPI.io. Retrieved2024-07-27.
  127. ^"oneAPI Specification — oneAPI Specification 1.3-rev-1 documentation".oneapi-spec.uxlfoundation.org. Retrieved2024-07-27.
  128. ^Cherney, Max A.; Cherney, Max A. (26 March 2024)."Exclusive: Behind the plot to break Nvidia's grip on AI by targeting software".Reuters. Retrieved2024-04-05.
  129. ^"Question: What does ROCm stand for? · Issue #1628 · RadeonOpenCompute/ROCm".Github.com. RetrievedJanuary 18, 2022.

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