 CDC 160-A with close-up of control panel | |
| Developer | Seymour Cray |
|---|---|
| Manufacturer | Control Data Corporation |
| Release date | 1960 (1960) |
| Introductory price | $100,000 equivalent to $1,062,880 in 2024 |
| Units shipped | 400 |
| Storage | 4096 words of magnetic core |
| Power | 115 V, 12 A |
| Dimensions | 29 by61+1⁄2 by 30 inches (740 mm × 1,560 mm × 760 mm) |
| Weight | 810 lb (370 kg) |
| Successor | CDC 6000 series |
TheCDC 160 series was a series ofminicomputers built byControl Data Corporation. The CDC 160 and CDC 160-A were 12-bit minicomputers[1][2] built from 1960 to 1965; the CDC 160G was a 13-bit minicomputer, with an extended version of the CDC 160-A instruction set, and a compatibility mode in which it did not use the 13th bit.[3] The 160 was designed bySeymour Cray - reportedly over a long three-day weekend.[4]It fit into the desk where its operator sat.
The 160 architecture usesones' complement arithmetic withend-around carry.[5]
NCR joint-marketed the 160-A under its own name for several years in the 1960s.[6]
A publishing company that purchased a CDC 160-A described it as "a single user machine with no batch processing capability. Programmers and/or users would go to the computer room, sit at the console, load the paper tape bootstrap and start up a program."[7]
The CDC 160-A was a simple piece of hardware, and yet provided a variety of features which were scaled-down capabilities found only on larger systems. It was therefore an ideal platform for introducing neophyte programmers to the sophisticated concepts of low-levelinput/output (I/O) andinterrupt systems.
All 160 systems had apaper-tape reader, and a punch, and most had anIBM Electric typewriter modified to act as acomputer terminal.[8][9][10] Memory on the 160 was 4096 12-bit words. The CPU had a 12-bitones' complement accumulator but no multiply or divide. There was a full complement of instructions and several addressing modes. Indirect addressing was almost as good as index registers. The instruction set supported both relative (to the current P register) and absolute. The original instruction set did not have a subroutine call instruction and could only address one bank of memory.[1]
In the 160-A model, a "return jump" and a memory bank-switch instruction was added. Return-jump allowed simple subroutine calls andbank switching allowed other 4K banks of memory to be addressed, albeit clumsily, up to a total of 32,768 words.[2] The extra memory was expensive and had to be contained in a separate box as large as the 160 itself. The 160-A model could also accept a multiply/divide unit, which was another large and expensive peripheral box.
In the 160 and 160-A, the memory cycle time was 6.4 microseconds. An add took two cycles. The average instruction took 15 microseconds, for a processing rate of 67,000 instructions per second.[1][2]
The 160G model extended the registers and memory words to 13 bits; in G mode, all 13 bits were used, while in A mode, only the lower 12 bits were used, for binary compatibility with the 160-A. The 160G added some instructions, including built-in multiply and divide instructions, and some additional addressing modes.[3][11]
Low-level I/O allowed control of devices, interfacing for determining device status, and for reading and writing data as either single bytes, or as blocks. I/O could be completed to a register, or to memory, or via adirect memory access (DMA) channel. The distinction between these I/O types was that regular I/O would 'hang' the CPU until the I/O operation completed, but DMA I/O allowed the CPU to proceed with instruction execution concurrently with the data transfer. The interrupt system was purely based on IO, meaning that all interrupts were generated externally. Interrupts were introduced to neophytes as being the alert mechanism by which a program could be informed that a previously initiated DMA I/O operation was completed.
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The 160 architecture was modified to become the basis of theperipheral processors (PPs) in theCDC 6000 series mainframe computers and its successors.[4] Large parts of the 160 instruction set were unchanged in the peripheral processors. However, there were changes to incorporate the 6000 data channel programming, and control of thecentral processor. In the early days of the 6000s, almost the entireoperating system ran in the PPs. This left the central processor unencumbered by operating system demands and available for user programs.
The CDC 160, rumored to have been designed over a weekend by Cray, was CDC's first $60,000desk (notdesktop) computer that became the prototype I/O processor for the peripheral processors surrounding the CDC 6600 and 7600.
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