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Incomputing,bus mastering is a feature supported by manybus architectures that enables a device connected to the bus to initiatedirect memory access (DMA) transactions. It is also referred to asfirst-party DMA, in contrast withthird-party DMA where a systemDMA controller actually does the transfer.
Some types of buses allow only one device (typically theCPU, or its proxy) to initiate transactions. Most modern bus architectures, such asPCI, allow multiple devices to bus master because it significantly improves performance for general-purposeoperating systems. Somereal-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency.
While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA tomain memory.
If multiple devices are able to master the bus, there needs to be abus arbitration scheme to prevent multiple devices attempting to drive the bus simultaneously. A number of different schemes are used for this; for exampleSCSI has a fixed priority for each SCSI ID. PCI does not specify the algorithm to use, leaving it up to the implementation to set priorities.
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |
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